Staff Engineer, Design Verification Engineering

Job Title

Staff Engineer, Design Verification Engineering

Role Summary

Responsible for architecting and implementing verification environments and plans for block-level and full-chip ASIC/SoC designs. Works on SystemVerilog/UVM testbenches, verification planning, coverage closure and integration of third-party and custom IP/VIPs.

Collaborates with design, evaluation and applications teams across the development lifecycle. Position includes a partial telecommute benefit (up to 2 days per week remote).

Experience Level

Senior — typical experience expectation: 4+ years with a Master’s degree or 6+ years with a Bachelor’s degree (per posted qualifications).

Responsibilities

Primary responsibilities include:

• Develop and execute UVM-based verification environments for block and full-chip ASIC/SoC designs.
• Create and implement verification plans and strategies, including constrained-random and directed tests.
• Write and analyze functional coverage, assertions, and verification metrics to measure progress and drive convergence.
• Integrate and verify third-party and custom IPs/VIPs within subsystem-level UVM environments and develop stimulus sequences and functional checkers.
• Debug simulations and analyze waveforms to locate and resolve design and testbench issues.
• Support post-silicon verification and collaborate with evaluation and applications engineering teams during bring-up.
• Automate simulation data analysis and model validation using scripting and design automation tools.
• Review test plans with cross-functional teams and ensure coverage closure.

Requirements

Must-have technical skills and experience:

• Proven expertise with SystemVerilog and UVM; experience building and maintaining metric-driven verification environments.
• Experience integrating UVM agents and Verification IP (VIP) and developing stimulus and functional checkers.
• Strong coverage-driven verification skills, including architecting coverage models and driving convergence.
• Experience developing assertions and analyzing functional coverage and verification metrics.
• Ability to debug simulations and analyze waveforms effectively.
• Scripting experience for automation and analysis (e.g., Python, Tcl) and familiarity with design automation tools.
• Effective collaboration and communication with design and cross-functional teams.

Education Requirements

Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering or a closely related technical field plus four (4) years of relevant design verification experience; OR Bachelor’s degree in the same fields plus six (6) years of relevant design verification experience. Foreign education equivalents are acceptable.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.