Staff Engineer, Design Verification

Job Title

Staff Engineer, Design Verification

Role Summary

Lead verification architecture, execution, and delivery for next-generation ASICs on Marvell's CXL product development team. Responsible for verification planning, emulation, post-silicon validation and lab bring-up while coordinating across RTL, physical design, firmware and system teams.

Experience Level

Senior — role expects extensive leadership and ASIC verification experience. The posting specifies senior experience levels (examples provided by degree: PhD: 12+ years; Master's: 18+ years; Bachelor's: 20+ years).

Responsibilities

The primary responsibilities focus on verification leadership for complex SoC/ASIC projects.

• Define and lead verification architecture and strategy for complex ASICs, including metrics, schedules and resource planning.
• Own verification execution across simulation, emulation and post-silicon validation (PSV) to meet tapeout and product quality goals.
• Drive emulation efforts and integrate emulation into the verification flow to accelerate closure and debug.
• Lead lab bring-up and post-silicon validation activities for multiple ASICs.
• Develop verification environments for SoC subsystems: processor cores, memory subsystems and peripheral interfaces.
• Collaborate with cross-functional teams (RTL, physical, firmware, systems, tools) to resolve complex issues and deliver products.
• Mentor and lead verification engineers; promote best practices, tools and methodologies.

Requirements

Key required skills and experience (education requirements are summarized separately below).

• Extensive, demonstrable experience leading verification and delivery of high-quality ASICs.
• Deep understanding of ASIC development processes, verification methodologies and common tools.
• Hands-on verification experience with multiple SoC architectures, processor cores, memory subsystems and peripheral interfaces.
• Practical experience with lab bring-up, post-silicon validation and emulation-driven verification flows.
• Proven leadership, strong communication and cross-functional collaboration skills.
• Self-motivated, able to drive adoption of new methodologies and tools across teams.
• Nice-to-have: experience with CXL or datacenter interconnects and familiarity with composable datacenter architectures.

Education Requirements

Degrees stated in the posting: Bachelor's degree in Computer Science, Electrical Engineering or related field (with ~20+ years’ experience); Master’s degree in Computer Science, Electrical Engineering or related field (with ~18+ years’ experience); PhD in Computer Science, Electrical Engineering or related field (with ~12+ years’ experience). Fields of study referenced: Computer Science, Electrical Engineering or related technical fields.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.