Staff Engineer - Design Verification

Job Title

Staff Engineer - Design Verification

Role Summary

Senior verification engineer responsible for planning and executing block, subsystem, and full-chip verification for mixed-signal SoCs targeting low-power IoT and edge-AI applications. Work within a cross-functional SoC design team to deliver verified silicon to specification.

Focus areas include SystemVerilog/UVM testbench architecture, SoC-level verification, power-aware methodologies, C-based verification, and debug/root-cause analysis.

Experience Level

Senior — typically 7–10+ years of design verification experience, including block, subsystem, and full-chip verification.

Responsibilities

The role owns verification deliverables and quality across module, subsystem, and full-chip scopes.

• Assume full ownership of design verification (DV) tasks and deliverables.
• Develop verification plans at block, sub-system, and chip levels.
• Architect and implement scalable, reusable SystemVerilog/UVM testbenches.
• Create C-based verification packages and tests for SoC environments.
• Execute SoC-based verification, including full-chip and module-level runs.
• Develop stimulus, checkers, and randomized test cases to achieve coverage goals.
• Automate test environments, score-boarding, and regression flows.
• Use advanced debug techniques and perform root-cause analysis; work with design teams to resolve issues.
• Define, track, and report functional and code coverage metrics.
• Ensure verification quality meets project and industry standards.

Requirements

Must-have technical skills and domain experience; concise list of preferred additional skills.

• Strong SystemVerilog and UVM expertise; Verilog proficiency.
• SoC verification experience — ARM or RISC-V processor-based designs preferred.
• Experience with AMBA protocols (AXI/AHB/APB), DMA, flow control, and 3rd-party IP integration.
• Power-aware verification experience (CPF/UPF) and low-power verification challenges.
• C-based verification in an SoC environment; familiarity with C/C++.
• Scripting and tooling: Python, Perl, Makefile or similar.
• Proven track record of delivering multiple chips to specification and managing DV schedules and risks.
• Strong collaboration and communication skills with design, architecture, and software teams.
• Nice-to-have: peripheral and subsystem experience (UART, SPI, I2C, audio, display, USB, OTP, crypto) and edge-AI inference exposure.

Education Requirements

Bachelor of Science or Master of Science in Electrical Engineering (BSEE/MSEE) is stated. The posting references 7–10+ years of relevant verification experience; no certifications or alternate-degree language explicitly provided.

About the Company

Company: Ambiq

Headquarters: Austin, TX, United States

Semiconductor company developing ultra-low-power microcontroller units (MCUs) and system-on-chip (SoC) platforms for battery-powered and edge devices, focusing on low-power IP, RTL, and production silicon solutions.