Staff Engineer - Design Verification

Job Title

Staff Engineer - Design Verification

Role Summary

Lead verification of complex CPU core microarchitecture to ensure functional correctness, performance, and silicon readiness. You will own end-to-end DV for core components and drive verification strategy, planning, and closure.

The role works closely with Architecture and Design teams on ISA- and microarchitecture-level validation for high-performance processors.

Experience Level

Senior — Staff level role. Requires 7+ years of design verification experience.

Responsibilities

The engineer will plan and execute verification activities across CPU core subsystems and manage closure.

• Own end-to-end verification of CPU core components (fetch, decode, execute, pipeline, memory, cache, MMU).
• Develop verification strategies and drive DV closure for microarchitectural features (out-of-order execution, branch prediction, cache coherency, virtual memory/paging).
• Create test plans from architecture specs and ensure full coverage closure.
• Design and implement testbenches, constrained-random tests, scoreboards, and checkers using SystemVerilog/UVM.
• Develop and maintain coverage models (functional and code) and drive regressions.
• Debug complex simulation and emulation failures and coordinate fixes with design teams.
• Perform ISA-level validation and compliance testing; validate corner cases, exceptions, and interrupts.
• Collaborate with architects and designers to interpret ISA behavior and validate features.

Requirements

Must-have technical skills and experience; concise list of essential and desirable qualifications.

• Must-have: 7+ years in design verification, with hands-on experience in SystemVerilog and UVM.
• Must-have: Strong experience verifying CPU microarchitecture and core components (OOO, branch prediction, cache coherency, MMU).
• Must-have: Proficiency writing testbenches, constrained-random tests, scoreboards, checkers, and coverage models.
• Must-have: Experience driving regressions, debugging complex failures across simulation and emulation platforms.
• Must-have: Practical knowledge of ISA behavior (examples: ARM, RISC-V, x86) and ISA-level validation.
• Must-have: Ability to lead verification strategy and coordinate cross-team verification activities.
• Nice-to-have: Hands-on experience with hardware emulation platforms and silicon bring-up.
• Nice-to-have: Prior experience in high-performance or data-center CPU projects.

Education Requirements

Bachelor's or Master's degree in Engineering (e.g., BE, BTech, MEng). The posting specifies a Bachelor's or Master's in Engineering.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.