Staff Engineer

Job Title

Staff Engineer

Role Summary

Staff Engineer responsible for formal verification of NoC and interconnect IP and subsystems. Work with design, architecture, and simulation/emulation teams to develop verification plans, property sets, and reusable formal environments that ensure correctness and coverage for complex SoC interconnects.

This role is based in Ahmedabad and requires successful background checks, proof of right to work in India, and export-control authorization where applicable.

Experience Level

Senior-level. Position requires 7+ years of relevant industry experience.

Responsibilities

Primary responsibilities focus on formal verification of interconnect and NoC components and driving closure of formal proofs and issues.

• Own formal verification for NoC/interconnect blocks (crossbars, arbiters, bus-blockers, on-/off-ramps, routing fabric).
• Develop formal verification plans and property suites at block and subsystem levels.
• Write SystemVerilog Assertions (SVA), assumptions, cover properties, and protocol checks.
• Build and maintain reusable formal verification environments, checkers, and scoreboarding infrastructure.
• Drive debug, root-cause analysis, and closure of formal counterexamples with design and architecture teams.
• Analyze proof convergence, constraint quality, and coverage gaps; improve methodology for scalability.
• Collaborate with simulation/emulation teams to ensure end-to-end verification closure.

Requirements

Must-have technical skills and experience; preferred items are listed separately.

• Strong experience in formal verification of RTL designs.
• Solid knowledge of SystemVerilog and SystemVerilog Assertions (SVA).
• Experience verifying interconnects, NoCs, coherent fabrics, or complex SoC subsystems.
• Good understanding of NoC building blocks: arbiters, routers, crossbars, flow control, buffering, protocol adapters.
• Experience debugging formal failures, constraint issues, and proof complexity.
• Strong problem-solving and communication skills.

Nice-to-have:

• Experience with coherent interconnect protocols and memory subsystem verification.
• Performance-oriented verification, simulation, or emulation experience.
• Familiarity with clock-domain crossing, reset verification, deadlock/livelock checks, and end-to-end data integrity properties.
• Scripting for automation (Python, Perl, Tcl).
• Experience defining verification strategy and signoff criteria for complex IP/subsystems.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field. The role expects significant industry experience (advertised as 7+ years).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.