Staff Engineer — CPU Hardware Verification (Power Management)
QualcommJob Title
Staff Engineer — CPU Hardware Verification (Power Management)
Role Summary
Senior verification engineer responsible for end-to-end verification of CPU co-processor power-management firmware-driven hardware features. The role sits within the Hardware Engineering organization and partners with Firmware, RTL design, emulation, and post-silicon teams to deliver silicon-ready power-management features.
Primary mission: define verification strategy, build scalable SystemVerilog/UVM testbenches and infrastructure, validate power-management scenarios (DVFS, low-power modes, clock/power transitions), and drive functional signoff.
Experience Level
Senior / Staff level. Preferred experience: 10–12+ years in CPU, GPU, SoC, or complex subsystem verification. Minimum experience varies by degree: Bachelor's +4 years, Master's +3 years, PhD +2 years (see Education Requirements).
Responsibilities
The role owns verification strategy, execution, and cross-functional coordination for power-management features.
- Lead end-to-end verification of CPU co-processor (CPUCP/PDP) firmware-driven power-management hardware features.
- Architect and develop SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructure for complex SoC subsystems.
- Verify AMBA-based system IPs: timers, mailboxes, interrupts, and interconnect fabrics (NoC).
- Plan verification, create test strategies, model coverage, close coverage gaps, and drive functional signoff.
- Define and validate DVFS, low-power modes (LPM), clock/power transitions, firmware-controlled sequences, and reset flows.
- Lead complex debug and root-cause analysis across Firmware, RTL, Emulation, and Post-Silicon teams.
- Develop reusable stimulus frameworks, automation solutions, debug utilities, dashboards, and productivity tools.
- Support platform bring-up, feature qualification, HW/FW release validation, and silicon readiness activities.
- Influence architecture reviews and verification methodologies and mentor junior engineers.
Requirements
Must-have technical skills, tools, and experience for immediate contribution.
- Extensive experience in SoC, CPU, or power-management verification environments.
- Strong expertise in SystemVerilog/UVM, verification methodologies, and testbench architecture.
- Proven experience developing NoC transactors, protocol checkers, and verification infrastructure.
- Deep understanding of AMBA protocols and system-level IPs (timers, mailboxes, interrupts, memory-mapped peripherals).
- Strong background in RTL simulation, emulation, waveform analysis, debug methodologies, and coverage closure.
- Experience validating DVFS, low-power modes, idle states, power sequencing, and reset flows.
- Proficiency in C/C++, SystemVerilog, Python, scripting, automation, and data-driven verification workflows.
- Strong analytical and debugging skills across hardware, firmware, and system domains; demonstrated ability to lead distributed technical teams.
- Nice-to-have: power-aware verification, gate-level simulation hands-on experience, CI/CD and regression automation frameworks.
Education Requirements
Required: Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, or a related engineering field. Minimum experience varies by degree: Bachelor's +4 years, Master's +3 years, PhD +2 years. Equivalent practical experience may be considered where explicitly stated.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
