Staff Engineer, ASIC STA

Job Title

Staff Engineer, ASIC STA

Role Summary

Work on processors, controller architectures and ASICs for Micron's Enterprise SSD group. Responsible for block- and chip-level synthesis, STA-driven timing closure, low-power intent verification, and tape-out activities for hierarchical SoC designs.

Experience Level

Senior — typically 8–14 years of relevant experience in synthesis and static timing analysis (STA).

Responsibilities

Key responsibilities include synthesis and timing closure for blocks and full-chip hierarchical designs, establishing constraints, and collaborating with cross-functional teams to achieve PPA and timing goals.

• Perform block and chip-tile synthesis to meet power, performance, and area (PPA) targets.
• Generate constraints and drive timing closure for block and full-chip hierarchical SoC across multiple modes.
• Collaborate with Design, DFT, IP and PD teams to resolve timing and constraint conflicts.
• Implement and verify low-power intent (CPF/UPF) with minimal supervision.
• Execute logical equivalence checks and low-power rule checks.
• Conduct early RTL analysis for clocking, power, and DFT coverage and recommend improvements.
• Support verification teams for gate-level simulation and timing sign-off.

Requirements

Must-have technical skills and tools experience followed by preferred skills.

• 8–14 years of hands-on experience in synthesis and STA.
• Proven experience across the RTL-to-GDSII flow, including floorplanning, placement, CTS, routing, RC extraction, and tape-out activities.
• Hands-on synthesis and STA on advanced process nodes using Synopsys and/or Cadence toolchains.
• Experience with constraints generation and timing closure for complex hierarchical designs.
• Experience with equivalence checking (Synopsys/Cadence) and understanding of timing budgets.
• Proficiency in scripting (Perl, Tcl, Python) for automation and flow integration.
• Experience with multi-voltage designs using CPF/UPF and power analysis using PTPX.
• Working knowledge of VHDL/Verilog constructs.

Nice-to-have:

• Experience with Cadence place-and-route tools.
• Formal verification experience.
• Background in digital electronics and microprocessor design.
• Strong verbal communication skills.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.