Staff DRAM RTL Design Engineer

Job Title

Staff DRAM RTL Design Engineer

Role Summary

Design and deliver RTL for DRAM/memory-related digital IP from microarchitecture through integration and silicon bring-up. Work across architecture, verification, CAD/EDA, physical design and software teams to enable full-chip sign-off and production-ready memory IP.

Experience Level

Senior - staff-level engineering role. The posting specifies experience in the senior range (see Education Requirements for explicit years guidance).

Responsibilities

Key technical and cross-functional responsibilities:

• Design digital IP blocks from microarchitecture to RTL, integration, and support for physical hardware development.
• Define and review module interfaces and system-level architecture.
• Leverage AI-based tools and automation to accelerate RTL optimization, design-space exploration, testbench generation, and debug across simulation and silicon learning loops.
• Define semicustom memory design methodology and drive SoC/ASIC semicustom flows.
• Lead full-chip integration activities including CDC, linting, synthesis, STA and power analysis.
• Collaborate with CAD, EDA, verification, architecture and physical design teams to integrate flows into simulation and sign-off environments.
• Oversee floor-planning, placement, routing and layout coordination with physical design teams.
• Perform block-level and full-chip verification: functional, timing, power and reliability analysis using industry and company tools.
• Provide technical mentorship and participate in design and methodology reviews to standardize and improve group processes.

Requirements

Must-have technical skills and capabilities:

• Proven RTL design experience and ability to deliver silicon-quality RTL implementations.
• Strong knowledge of asynchronous and synchronous design concepts and CDC methodologies.
• Deep understanding of SoC design flows: lint, CDC, synthesis, static timing analysis and power analysis.
• Fundamentals in CMOS circuit behavior, device physics and memory operation (applied knowledge expected).
• Experience working effectively with global, multi-functional teams.

Nice-to-have:

• Domain experience with DRAM protocols (DDR5, LPDDR5, HBM) or other memory technologies.
• Familiarity or strong interest in AI/ML-assisted design flows, agentic AI or advanced automation for digital design and verification.
• Experience with Spyglass or similar lint/verification tools.
• Experience on NAND memory design or full SoC/ASIC semicustom flows.

Education Requirements

Master's degree in Electrical Engineering or Computer Engineering is specified in the posting; the role indicates 6–10 years of RTL design experience. Fields mentioned: electrical or computer engineering, with expectations of memory and CMOS fundamentals. (This degree and years requirement was taken from the posting.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.