Staff Digital Verification Engineer – UVM/SystemVerilog

Job Title

Staff Digital Verification Engineer – UVM/SystemVerilog

Role Summary

Senior verification engineer responsible for developing SystemVerilog/UVM testbenches and verification plans for high-speed PHYs, controllers, and chiplets at an early-stage semiconductor startup.

Work on cross-functional teams to deliver manufacturable, high-performance connectivity IPs and lead verification best practices and automation efforts.

Experience Level

Senior level. Requires 6+ years of experience in digital verification, including hands-on protocol verification and technical leadership responsibilities.

Responsibilities

Primary responsibilities include verification planning, environment development, and mentoring junior engineers.

• Develop and execute verification plans for connectivity IPs and chiplets (unit and chip level).
• Create and maintain SystemVerilog/UVM verification environments and compliant test cases.
• Maintain regression infrastructure to support CI/CD pipelines and coverage tracking.
• Collaborate with design engineers on microarchitecture, test-plan, and coverage reviews to ensure design quality.
• Track test-plan items and progress toward RTL freeze.
• Ensure IP compliance with Ethernet standards (IEEE 802.3) and relevant clauses for high-speed links.
• Integrate third-party VIPs and coordinate feature/bug tracking with vendors.
• Act as a technical lead and mentor for junior verification engineers.
• Develop and maintain simulation environments, including DPI-based firmware simulations and GLS setups for functional and power verification.

Requirements

Must-have technical skills and experience are listed first; additional desirable skills follow.

Must-have:

• Hands-on experience verifying serial transmission protocols and products (e.g., retimer, gearbox, Ethernet PMA/PCS logic).
• Strong expertise in UVM and SystemVerilog, including test environment and assertion coding.
• Proficiency with third-party tools for regression management and coverage analysis.
• Experience with Ethernet 802.3 clauses for 100G, 200G, 400G, and 800G; knowledge of Auto-Negotiation and Link Training (3+ years on Ethernet clauses preferred).
• Experience verifying third-party mixed-signal IPs and integrating VIPs into verification environments.
• Demonstrated focus on automation and process improvements to increase verification quality and efficiency.
• Proven ability to operate in a fast-paced, early-stage startup environment and mentor junior engineers.

Nice-to-have:

• Familiarity with DRAM controllers/PHYs and HBM memory.

Education Requirements

Master's or Ph.D. in Electrical Engineering or a closely related field. The role specifies 6+ years of relevant verification experience.

About the Company

Company: Beacon Industries

Technology/engineering company focused on analog and mixed-signal integrated circuit design and custom IC layout (SerDes, SRAM, high-speed interfaces), using Synopsys/Cadence EDA tools for design, simulation, verification, and silicon validation.