Staff Digital Verification Engineer

Job Title

Staff Digital Verification Engineer

Role Summary

Lead verification for DesignWare IP, building scalable SystemVerilog/UVM environments and owning verification closure for critical PHY and interface blocks. Work closely with RTL designers, architects, and circuit teams to define verification scope, drive metric-based signoff, and ensure IP quality before tapeout.

Experience Level

Senior - the posting specifies 4+ years of hands-on verification experience.

Responsibilities

Primary duties include designing verification strategies, developing testbenches, and driving closure across multiple blocks.

• Build and evolve SystemVerilog/UVM verification environments that scale across product generations and configurations.
• Define comprehensive test plans covering corner cases, protocol compliance, and system-level interactions for serial interfaces and memory controllers.
• Write and debug testbenches, checkers, and assertions targeting real bugs in PHY blocks and interface logic.
• Own verification closure for multiple DDR PHY blocks, including functional coverage, code coverage, and formal signoff.
• Collaborate with RTL designers, architects, and circuit teams to align verification with design intent and surface issues early.
• Manage regression infrastructure, optimize verification cycles, and ensure reliable, usable environments for the team.

Requirements

Essential technical skills and delivery experience; degree requirements are summarized separately below.

• Must-have: Deep experience developing SystemVerilog/UVM testbenches, assertions, and checkers from scratch and evolving them as designs grow.
• Must-have: Proven track record leading verification efforts through IP delivery, including planning, execution, and signoff.
• Must-have: Proficiency extracting and using functional and code coverage metrics to drive closure and perform formal signoff activities.
• Must-have: Strong debugging skills and experience collaborating with RTL designers and architects to resolve verification/design issues.
• Preferred: Experience verifying serial interface protocols and memory controllers; knowledge of DDR/LPDDR is a strong plus.
• Preferred: Experience with PHY verification and AI-assisted verification tools.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Electronics and Communication Engineering. The posting specifies 4+ years of hands-on verification experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.