Staff Digital Verification Engineer

Job Title

Staff Digital Verification Engineer

Role Summary

Lead digital verification and contribute to RTL design and verification infrastructure for ASICs and FPGAs. Serve as technical lead for one or more devices or subsystems and coordinate with Design, ATE, Application and Systems teams.

Support pre- and post-silicon validation, debug, and delivery of production-quality digital IP and chip-level blocks.

Experience Level

Senior - staff-level role. Posting requests a minimum of 5+ years in ASIC or FPGA design and verification.

Responsibilities

Primary responsibilities include ownership of verification strategy, implementation, and delivery.

• Develop verification plans, testbenches, automated regression tests, and coverage tracking.
• Lead RTL design work from concept through implementation for ASIC/FPGA blocks.
• Debug design and verification failures; support post-silicon bring-up and validation.
• Drive synthesis, timing closure, formal verification and gate-level verification activities.
• Create and maintain scripts and automation for design and verification flows.
• Estimate tasks, manage schedules, and coordinate cross-functional verification activities.
• Collaborate with Design, ATE, Application and Systems groups to integrate and validate features.

Requirements

Must-have technical skills and experience for successful performance in the role.

• 5+ years experience in digital design and verification of ASICs or FPGAs.
• Proficient in digital verification languages and methodologies: Verilog, SystemVerilog, UVM and automated regression development.
• Strong knowledge of digital design techniques and the ASIC development process.
• Practical experience across the digital design flow: RTL verification, synthesis, place-and-route, gate-level verification, power estimation, ATPG and AMS simulations.
• Experience with industry-standard EDA tools: digital simulators, synthesis tools, STA, DFT, LEC, and formal verification.
• Proficient in scripting and programming for automation: Python, TCL, Perl, shell, C/C++.
• Good written and verbal communication skills, and proven teamwork and technical leadership.

Nice-to-have:

• Embedded design or firmware experience.
• Familiarity with JEDEC, Automotive FuSA and ASIL standards.
• Experience with DDR, power-management ICs, and common serial interfaces (I2C, I3C, SPI, USB, PMBUS).
• Experience with GITLab or similar CI/CD and source-control tools.

Education Requirements

PhD, MS or BS in Electrical Engineering (digital design/VLSI emphasis) - the posting lists PhD/BS/MS in Electrical Engineering with Digital Design/VLSI coursework.

About the Company

Company: Monolithic Power Systems

Headquarters: San Jose, California, USA

Monolithic Power Systems, Inc. (MPS) is a leading provider of energy-efficient power solutions for various applications, including industrial, telecom, automotive, and consumer sectors. Known for their cutting-edge integrated power semiconductors, MPS emphasizes innovation, sustainability, and creativity, making them one of the fastest-growing companies in the semiconductor industry.