Staff Digital Physical Implementation and Integration Engineer

Job Title

Staff Digital Physical Implementation and Integration Engineer

Role Summary

Own physical implementation and top-level integration for large digital designs in NAND/memory products. Drive partitions and full-chip assemblies from synthesis handoff through floorplanning, place-and-route, timing closure, DRC/LVS, and sign-off.

Work cross-functionally with Product Engineering, Test, Process Integration, Assembly, CAD, STA, DFT and custom-layout teams to ensure manufacturability, performance, and timely tape-outs. Contribute to methodology and automation.

Experience Level

Senior-level — typically requires 5+ years of digital physical design experience and at least one full tapeout owned end-to-end.

Responsibilities

Primary responsibilities include physical implementation, top-level assembly, and enabling block handoffs.

• Perform design planning and top-level integration: virtual-flat placement, global routing, partition creation, pin optimization, repeater/feedthrough planning, and power-domain planning.
• Drive top-level assembly and closure: integrate LEF/DEF/GDS/ETM/ILM, close timing, DRC/LVS, EM/IR, and iterate ECOs to convergence.
• Implement block-level APR flow (floorplan → place → CTS → route → ECO → sign-off) and own block-level STA sign-off across corners.
• Generate and hand off block constraints (timing budgets, boundary SDC, ILM/ETM models, physical constraints) from planning tools to block owners.
• Debug and correlate synthesis vs. APR vs. STA; manage PPA regressions, scan stitching, and ECO strategies.
• Automate flows and tooling in Tcl, SKILL, and Python; extend make-based flows and contribute to shared analysis tooling and dashboards.
• Collaborate with CAD, STA, DFT, custom-layout, Test, and Process Integration to ensure manufacturability and quality.
• Provide mentorship and documentation for methodology, and adopt/extend internal AI-assisted engineering tools.

Requirements

Must-have technical skills and experience for immediate contribution.

• 5+ years of digital physical design experience with at least one full tapeout owned end-to-end.
• Strong static timing analysis and debugging skills; fluent with PrimeTime across MMMC and OCV/AOCV/POCV; experience with ILM/ETM block abstractions and ECO fixing.
• Hands-on experience with Cadence Innovus Hierarchical Flow or Synopsys ICC2 Design Planning (virtual-flat, partitioning, pin optimization, budgeting, assembly).
• Strong flat APR expertise with Innovus or ICC2: floorplan, place, CTS, route, ECO, and sign-off correlation.
• Synthesis proficiency with Design Compiler or Genus and familiarity with size_only, don't_touch, MBFF, scan, and clock gating strategies.
• Physical verification experience with Calibre (DRC, LVS, antenna, PERC) and waiver management; hierarchical and flat runs.
• SDC authoring for multi-mode/multi-corner designs and ability to derive block budgets from top-level planning.
• Fluent in Tcl and at least one of Python or Perl for flow automation; experience with Linux/Unix, Git or similar VCS, and make-based flows.
• Working proficiency with agentic AI applied to engineering workflows and internal AI toolkits; able to use and extend AI tooling from day one.
• Solid understanding of CMOS logic, standard cells, RC extraction, EM/IR, and low-power techniques (multi-voltage, power gating, retention).

Nice-to-have:

• Experience with multi-partition SoC or memory top-level integration and driving ECOs across hierarchies of 5+ blocks.
• Clock planning at the top level and memory (NAND/DRAM) or mixed-signal collaboration experience.
• Familiarity with DFT/scan compression, JTAG, MBIST; EDA vendor AI tools (Cadence Cerebrus, Synopsys DSO.ai) and methodology/CAD contributions.

Education Requirements

Bachelor’s degree in Computer Engineering or Electrical Engineering is required. Master’s degree or Ph.D. in Computer Engineering or Electrical Engineering is preferred.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.