Staff Digital Physical Implementation and Integration Engineer

Job Title

Staff Digital Physical Implementation and Integration Engineer

Role Summary

Responsible for physical implementation and top-level integration of large digital designs for NAND memory products. The role drives partitions and full-chip flows from synthesis handoff through floorplan, place-and-route, timing closure, and sign-off, and coordinates with verification, CAD, process, test, and product engineering teams.

Experience Level

Senior — requires 5+ years of digital physical design experience and ownership of at least one full tapeout end-to-end.

Responsibilities

Deliver physical implementation, integration, and verification for large digital partitions and full-chip assemblies; automate and document flows; collaborate across design, verification, test, and manufacturing teams.

• Plan and execute top-level partitioning, virtual-flat placement, global routing, and top-level assembly to close timing, DRC/LVS, and EM/IR.
• Create and hand off block-level constraints (timing budgets, boundary SDC, ILM/ETM models) to block owners.
• Implement full APR flow on digital blocks (floorplan → place → CTS → route → ECO → sign-off) and own block-level STA sign-off across corners.
• Drive pin optimization, repeater/feedthrough insertion, and power-domain planning during partitioning and assembly.
• Debug and correlate synthesis, APR, and STA results; manage ECO iterations to convergence.
• Automate flows and tooling in Tcl, SKILL, and Python; extend shared analysis tooling and dashboards.
• Coordinate with STA, DFT, CAD, custom-layout, process integration, test, and product engineering to ensure manufacturability and quality.
• Mentor junior engineers and document methodology and best practices.

Requirements

Key technical requirements and skills for successful candidates.

• 5+ years of digital physical design with at least one full tapeout owned end-to-end.
• Strong static timing analysis and debug skills; fluent with PrimeTime across MMMC and OCV/AOCV/POCV, ILM/ETM abstractions, and ECO fixing.
• Hands-on experience with Cadence Innovus Hierarchical Flow or Synopsys ICC2 Design Planning (virtual flat, partitioning, pin optimization, budgeting, assembly).
• Proven top-level digital integration experience driving large-partition or full-chip designs from planning through assembly and hand-off.
• Strong flat APR expertise with Innovus or ICC2: floorplan, place, CTS, route, ECO, and sign-off correlation.
• Synthesis experience with Design Compiler or Genus, including topographical/physical flows and scan/clock-gating strategies.
• Physical verification experience with Calibre (DRC, LVS, antenna, PERC) and waiver management.
• SDC authoring for multi-mode/multi-corner designs and ability to derive/validate block budgets from top-level planning.
• Fluent in Tcl and one of Python or Perl for flow automation; experience with Linux/Unix, Git (or VCS), and Make-based flows.
• Working proficiency with agentic AI applied to engineering workflows and ability to use/extend internal AI toolkits from day one.

• Multi-partition SoC or memory top-level integration experience; ECO coordination across 5+ blocks.
• Master's or Ph.D. in relevant fields (see Education Requirements).
• Clock planning at top level, memory (NAND/DRAM) or mixed-signal exposure, DFT/scan compression experience.
• Familiarity with EDA AI tools (Cadence Cerebrus, Synopsys DSO.ai) and contributions to methodology or CAD tooling.

Education Requirements

Bachelor's degree in Computer Engineering or Electrical Engineering is required. A Master's or Ph.D. in Computer Engineering, Electrical Engineering, or a closely related field is preferred.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.