Staff Digital Engineer (DFT Design)
RenesasJob Title
Staff Digital Engineer (DFT Design)
Role Summary
Join the Power Management IC team in Renesas' Automotive Business Unit to lead digital DFT efforts for automotive PMIC designs. The role focuses on implementing and validating DFT/scan, LogicBIST, and test patterns across pre- and post-layout flows and coordinating with test and validation teams to meet automotive test and ASIL requirements.
Onsite presence is required three days per week; you will work closely with architects, digital design, P&R, test engineering and silicon validation teams.
Experience Level
Senior (Staff). See Education Requirements for specific years-of-experience guidance.
Responsibilities
Key responsibilities include implementing and validating DFT solutions and collaborating across design and test disciplines.
- Insert DFT/scan on digital logic, run ATPG, and validate test patterns on pre- and post-layout gate-level netlists.
- Deliver test patterns to Test Engineering and support silicon validation of those patterns.
- Insert and validate LogicBIST using industry-standard tools.
- Improve scan coverage and modify RTL for scanability; reduce overall test time.
- Participate across the full digital flow: micro-architecture, partitioning, RTL (Verilog/SystemVerilog), timing constraints, synthesis, P&R interaction, timing analysis, lint, CDC.
- Assist with top-level testbench creation and gate-level simulations for scan testing.
- Develop DFT specifications, design documentation, and complete design-review checklists.
Requirements
Must-have technical skills and demonstrated hands-on experience; desirable items listed separately.
- Hands-on experience with scan insertion, ATPG, and validating test patterns on silicon.
- Practical experience with LogicBIST and industry-standard DFT flows.
- Gate-level simulation experience with test patterns and collaboration with test teams.
- RTL coding experience and exposure to synthesis and timing closure.
- Participation in at least two tapeouts with DFT/scan responsibilities.
- Experience with Synopsys, Cadence, Mentor tools; familiarity with Tetramax is a strong plus.
- Strong attention to detail, accuracy, and cross-functional communication skills.
Nice-to-have:
- Exposure to automotive test standards and ASIL-B/D requirements.
- Knowledge of Verilog-AMS, SystemVerilog, revision control (GIT, SVN), and interfaces like I2C, SPI, AMBA.
- Domain knowledge of PMICs and regulators; experience across multiple tapeout cycles from spec to mass production.
Education Requirements
Bachelor of Science in Electrical Engineering (BSEE) required; Master of Science in Electrical Engineering (MSEE) preferred. The posting specifies experience alternatives: MSEE +6 years or BSEE +8 years of relevant digital DFT experience. Fields referenced include Electrical Engineering and related digital design backgrounds; equivalent practical experience is acknowledged via the experience-based guidance.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
