Staff Digital Design Engineer – SoC Low Power, Clocking & Integration

Job Title

Staff Digital Design Engineer – SoC Low Power, Clocking & Integration

Role Summary

Join the IoT Digital Design team to architect and deliver highly integrated, low-power Wireless MCU SoCs. The role focuses on SoC-level low-power architecture, clocking infrastructure, RTL design and integration, and silicon bring-up for wireless IoT products.

You will work across architecture, RTL, verification, backend, and system bring-up, leading small teams to meet performance, power, and integration targets.

Experience Level

Senior — 10–20 years of professional experience in digital CMOS IC design and SoC integration.

Responsibilities

Primary responsibilities include SoC architecture, RTL development, low-power and clocking design, and system integration.

• Develop complex SoC architectures with multiple processors, digital/mixed-signal subsystems, and multiple power and clock domains.
• Define and implement SoC-level low-power architecture: power domains, retention, isolation, level shifters, and power sequencing.
• Develop and integrate UPF/CPF-based power intent across subsystem and SoC hierarchies.
• Design and integrate clocking infrastructure: clock generation, distribution, gating, muxing, reset architectures, and monitoring.
• Drive RTL design and integration of power, clock, and reset controllers and related infrastructure IP.
• Architect and integrate on-chip interconnects and bus fabrics (AXI, AHB, APB) and ensure protocol correctness.
• Analyze and debug low-power, clocking, CDC/RDC, timing, and protocol issues during simulation, emulation, synthesis, and silicon bring-up.
• Lead small design teams to architect, design, verify digital subsystems, and coordinate subsystem/SoC integration activities.
• Collaborate with backend, analog/mixed-signal, and verification teams to optimize power, performance, area, and ensure successful silicon validation.
• Support validation and bring-up of designs on silicon and provide cross-functional technical support.

Requirements

Must-have technical skills and experience for immediate contribution.

• Proven ability to lead small teams designing complex digital subsystems and drive integration activities.
• Strong RTL design expertise in Verilog/SystemVerilog; experience with RTL and gate-level simulation and waveform debug.
• Deep knowledge of SoC clocking architectures, CDC/RDC, synchronization techniques, and timing closure practices.
• Extensive experience with low-power design methodologies (UPF, power gating, retention, isolation, level shifting) and power-aware verification.
• Experience with on-chip bus protocols and interconnects (AXI, AHB, APB) and integrating third-party IP and processor clusters.
• Practical experience with logic synthesis, timing constraints, power analysis tools, and collaboration with backend teams for PPA optimization.
• Familiarity with embedded processor systems and C programming for integration and verification tasks.
• Scripting and automation skills (Python, Perl, Tcl) and experience with revision control/configuration management (Perforce, Git, Methodics).
• Excellent written and verbal communication skills and a demonstrated ability to deliver high output independently.
• Experience using AI-powered tools to enhance productivity and analysis is a plus.

Education Requirements

BS or MS in Electrical Engineering (as stated in the posting).

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.