Staff Digital Design Engineer – SoC Low Power, Clocking & Integration

Job Title

Staff Digital Design Engineer – SoC Low Power, Clocking & Integration

Role Summary

The Staff Digital Design Engineer will define and implement low-power SoC and clocking architectures, lead RTL design and subsystem integration, and support silicon validation for highly integrated wireless MCU SoCs. The role sits on the IoT Digital Design team working across architects, verification, backend, analog/mixed-signal, and software teams.

Primary focus areas are SoC low-power design (UPF/CPF-based intent), clocking infrastructure and distribution, RTL infrastructure IP (power/clock/reset controllers), interconnects, and integration/bring-up.

Experience Level

Senior — typically 10–20 years of professional experience in digital CMOS IC design (experience range provided by employer).

Responsibilities

Key responsibilities include:

• Architect and implement SoC-level low-power strategies: power domains, retention, isolation, level shifters, and sequencing.
• Design and integrate clocking infrastructure: clock generation, distribution, gating, muxing, reset architectures, and monitoring.
• Develop RTL for power management controllers, clock/reset controllers, DMA engines and bus fabric components.
• Integrate UPF/CPF power intent across subsystem and SoC hierarchies and drive power-aware verification.
• Architect and integrate on-chip interconnects and bus fabrics (AXI, AHB, APB) and third-party IPs.
• Analyze and debug CDC/RDC, clocking, timing, power, and protocol-related issues from simulation through silicon bring-up.
• Lead small teams of design engineers through architecture, design, review, verification, and integration phases.
• Collaborate with backend and analog/mixed-signal teams to optimize designs for power, performance, and area.
• Support validation and bring-up of designs on silicon and provide cross-functional support during bring-up.

Requirements

Must-have technical skills and experience:

• Proven ability to lead small teams designing complex digital subsystems and SoCs.
• Strong RTL design expertise in Verilog/SystemVerilog.
• Deep understanding of SoC clocking architectures, CDC/RDC, synchronization techniques, and timing considerations.
• Extensive experience with low-power design methodologies, including UPF, power gating, retention, isolation, and power-aware verification.
• Experience with on-chip bus protocols and interconnects (AXI, AHB, APB) and integrating processor clusters, memory subsystems, and third-party IPs.
• Experience with RTL and gate-level simulation, waveform/debug tools, power analysis, logic synthesis, and timing constraints.
• Familiarity with embedded processor systems and C coding for integration/bring-up tasks.
• Scripting and automation skills (Python, Perl, Tcl) and experience with revision control (Perforce, Git, Methodics).
• Strong written and verbal communication skills and ability to work independently.

Nice-to-have:

• Experience with analog/mixed-signal integration and verification in SoCs.
• Experience using AI-powered tools to enhance productivity and analysis.

Education Requirements

BS or MS in Electrical Engineering is specified. The posting also indicates ~10–20 years of professional digital CMOS IC design experience.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.