Staff Digital Design Engineer, HBM

Job Title

Staff Digital Design Engineer, HBM

Role Summary

Contribute to the architecture, RTL development, verification, and delivery of high-performance digital logic blocks for HBM memory products. Work across teams to achieve robust, tapeout-ready designs.

Translate specifications into Verilog/SystemVerilog RTL, evaluate tradeoffs across power, performance, and area, and drive design decisions through documentation and cross-team collaboration.

Experience Level

Senior-level. The posting indicates a minimum of ~3–5 years and preferred 5–10 years of related experience; the "Staff" title denotes senior responsibilities.

Responsibilities

Primary responsibilities include end-to-end digital design and delivery:

• Lead concept definition, specification, RTL implementation, documentation, verification support, and post-silicon debug.
• Develop scalable, parameterized Verilog/SystemVerilog RTL aligned to architectural specifications.
• Define and refine micro-architecture: FSMs, datapath, FIFOs, pipelines, and arbitration logic.
• Analyze tradeoffs in area, power, latency, and throughput and document decisions.
• Perform CDC/RDC analysis and implement clocking and reset strategies to mitigate timing issues.
• Support synthesis and static timing analysis, including SDC constraints and timing report interpretation.
• Apply low-power methodologies (CPF/UPF, clock gating, multi-domain partitioning, isolation/level shifters).
• Collaborate with verification, DFT, physical design, and CAD for design closure, scan/ATPG readiness, and formal/functional verification support.

Requirements

Must-have technical skills and experience:

• Proven RTL design proficiency in Verilog/SystemVerilog, with ability to translate specifications into maintainable micro-architecture and RTL.
• Strong digital logic fundamentals: FSMs, pipelines, datapath/control partitioning, buffering and flow control.
• Experience with synthesis, static timing analysis (STA), CDC/RDC investigation, and creating timing constraints.
• Proficiency in Linux and scripting (Python and/or Perl) to automate flows.
• Practical experience balancing power, performance, and area tradeoffs.
• Effective technical communication and cross-team collaboration skills.

Nice-to-have:

• Knowledge of memory system concepts (DRAM/SRAM), ECC/CRC, and DFT methodologies including memory/logic BIST.
• Experience with AMBA/AXI/APB protocols and working with custom or third-party macro models.

Education Requirements

Minimum: Bachelor’s degree in Electrical Engineering or equivalent practical experience. Preferred: Master’s degree in Electrical/Computer Engineering. Fields cited include Electrical/Computer Engineering or related technical disciplines; equivalent experience accepted.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.