Job Title
Staff Digital Design Engineer
Role Summary
Design and verify digital blocks for ASIC/IC products, covering RTL through post-layout verification. Work on digital backend flows and collaborate with place-and-route, analog, test, and application teams to deliver silicon-ready designs and prototypes.
Experience Level
Senior β 7+ years of ASIC/IC design experience.
Responsibilities
Key responsibilities include:
- Architect and implement optimized digital blocks that meet functional, cost, and low-power targets.
- Perform digital backend tasks: synthesis, UPF power intent, static timing analysis (STA), and logic equivalence checking (LEC).
- Prepare and hand off design constraints and deliverables to P&R; support post-layout checks and timing closure.
- Interface with place-and-route and participate in post-layout verification and sign-off activities.
- Collaborate with analog and test engineers on testability, debug, and silicon bring-up.
- Develop and validate FPGA prototypes; support lab debugging and physical silicon evaluation.
Requirements
Must-have and preferred qualifications.
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Must-have: 7+ years of ASIC/IC design experience across the RTL-to-silicon flow including RTL coding, synthesis, STA, LEC, and post-layout verification.
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Must-have: Fluent in Verilog RTL and ASIC design methodology; able to develop synthesis, STA, and P&R constraints.
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Must-have: Able to work independently and as part of a cross-functional team; strong communication and organizational skills.
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Nice-to-have: Experience with DFT or physical design.
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Nice-to-have: Experience with FPGA prototyping, lab equipment, and silicon lab debug.
Education Requirements
Not specified.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

Date Posted: 2026-06-09