Staff Digital Design Engineer

Job Title

Staff Digital Design Engineer

Role Summary

Design power- and area-optimized digital circuits for mixed-signal data-conversion and power-management products in advanced process nodes. Lead technical direction for the digital design team, support the full product lifecycle from architecture through mass production, and collaborate closely with analog, verification, and P&R teams.

Experience Level

Senior — requires more than 10 years of digital design experience in areas such as wireless handheld, data conversion, or power management.

Responsibilities

Deliver RTL and top-level digital integration for mixed-signal ASICs and support verification, timing closure, and silicon bring-up.

• Translate high-level requirements into micro-architecture and RTL implementations focused on low power and small area.
• Design RTL (Verilog/SystemVerilog) that meets timing, area, power and standards requirements.
• Integrate blocks at top level, run block- and top-level simulations, and assist with RTL and gate-level debug.
• Create timing constraints, drive synthesis, and interact with place-and-route teams for timing/area/power closure.
• Use lint, CDC, and RDC tools and participate in timing analysis (STA) and closure activities.
• Support DFT strategy and review test case development.
• Develop block- and chip-level design documentation and participate in design reviews and checklists.
• Support analog team with AMS or behavioral models and collaborate on complex pre-silicon verification scenarios.
• Perform silicon evaluation, document errata, and implement engineering change workarounds as needed.

Requirements

Must-have technical skills and behavioral expectations, plus preferred experience where indicated.

• Must-have: Extensive digital design experience (>10 years) in ASICs for data conversion, power management, or wireless handheld domains.
• Fluent in Verilog / SystemVerilog RTL for CMOS digital design.
• Strong understanding of ASIC design methodology, lint, CDC and RDC tools.
• Proven ability to debug RTL and gate-level simulations and to define/verify block- and chip-level verification strategies.
• Experience collaborating with P&R teams and generating design constraints for timing closure.
• Excellent written and verbal English communication skills.
• Willingness and ability to travel domestically or internationally on short notice; able to work independently and within cross-functional teams.

• Nice-to-have: Experience with DSP hardware concepts, flow/methodology automation and scripting, mixed-signal design methods, STA and timing closure, low-power techniques (clock/power gating, UPF), power analysis/optimization, advanced verification methodologies (UVM), and industry protocols such as AMBA or I2C.

Education Requirements

Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.