Staff DFT Engineer, Zhubei

Job Title

Staff DFT Engineer, Zhubei

Role Summary

Senior digital design engineer responsible for defining and implementing design-for-test (DFT) architecture for complex SoC/ASIC projects. The role partners with design, timing, and test engineering teams to deliver scan, MBIST, and boundary-test solutions and to enable production test bring-up.

Experience Level

Senior-level — requires 5+ years of hands-on experience in DFT architecture and implementation for SoC/ASIC.

Responsibilities

Design and implement DFT features across hierarchical SoC blocks, validate test strategies, and support production test.

• Define and implement hierarchical DFT architecture for complex SoC designs.
• Implement scan structures including stuck-at, at-speed, and path-delay tests.
• Design and integrate scan compression and boundary-scan solutions.
• Develop and validate MBIST for embedded memories, including low-power variants.
• Perform test time and test coverage analysis for scan and MBIST patterns.
• Develop scan ATPG and MBIST testbenches and run simulations in pre- and post-layout environments.
• Collaborate with test engineering to bring up production test programs.
• Work with timing and constraints teams to ensure DFT timing closure and correct constraint development.

Requirements

Core skills and experience required for success in this role.

Must-have:

• 5+ years hands-on experience in DFT architecture and implementation for SoC/ASIC.
• Proven experience with scan methodologies (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Experience with MBIST design and validation, including low-power MBIST techniques.
• Experience creating and implementing hierarchical DFT architectures in complex SoCs.
• Experience in test time and test coverage analysis for scan and MBIST patterns.
• Experience developing scan ATPG and MBIST test benches and running pre/post-layout simulations.
• Experience working with test engineering teams for production test program bring-up.
• Strong knowledge of timing concepts and constraint development; RTL experience required.

Nice-to-have:

• Experience with low-power DFT techniques in power-managed designs.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.