Staff Design Verification Engineer – High Performance CPU Core

Job Title

Staff Design Verification Engineer – High Performance CPU Core

Role Summary

Senior individual-contributor in the CPU Design Verification organization responsible for verification of high-performance out-of-order CPU core units. Focus areas include Frontend, Midcore, Load-Store Unit, and Hardware Prefetch.

Work with architecture, RTL, performance, and verification teams to define verification strategy, identify risks early, and deliver signoff-quality verification results.

Experience Level

Senior — typically requires 7+ years of relevant ASIC/CPU/core or SoC design verification experience.

Responsibilities

Accountable for verification planning and execution for complex CPU core features and interactions.

• Own verification planning, execution, coverage analysis, and closure for one or more high-performance core areas (e.g., Frontend, Midcore, LSU, Hardware Prefetch).
• Define verification strategies for instruction fetch, branch prediction, issue/dispatch, pipeline interactions, load/store ordering, hazard handling, memory consistency, and prefetch correctness.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to expose corner cases.
• Drive failure analysis and root-cause debug across specification, RTL, tests, and infrastructure.
• Collaborate early with architecture and design teams to review specs, reduce ambiguity, and improve debugability.
• Contribute reusable methodology, infrastructure, and technical guidance across core generations.

Requirements

Must-have technical skills and proven experience for delivering complex CPU verification.

• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Direct experience verifying CPU/core functionality and strong understanding of computer architecture and microarchitecture.
• Expertise in verification flow: test planning, constrained-random or directed stimulus, failure analysis, coverage analysis, and coverage closure.
• Proven debug skills and ability to translate architectural intent into verification strategy.
• Experience with verification of high-performance CPU features such as memory ordering/consistency and hardware prefetch.

Preferred / nice-to-have

• Experience with out-of-order core verification.
• Experience using formal verification and/or emulation for high-risk or performance-sensitive problems.
• Experience collaborating with performance, compiler, system verification, and software teams.
• Mentoring experience and influence on verification methodology beyond a single block.
• Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (BS/MS). Degree requirement explicitly listed in the posting.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.