Staff Design Verification Engineer – High Performance CPU Core
SiFiveJob Title
Staff Design Verification Engineer – High Performance CPU Core
Role Summary
Senior individual-contributor role in the CPU Design Verification organization focused on verification of high-performance out-of-order CPU core units (frontend, midcore, load-store, hardware prefetch and related core interactions).
The engineer will define verification strategy, plan and execute block- and core-level verification, drive debug and coverage closure, and collaborate with architecture, RTL, performance, and verification teams to reach signoff quality.
Experience Level
Senior - typically 7+ years of relevant ASIC/CPU/core/SoC design verification experience.
Responsibilities
Primary responsibilities include ownership of verification planning and delivery for complex CPU core features and improving verification quality and methodology across teams.
- Own verification planning and execution for one or more high-performance CPU core areas (Frontend, Midcore, Load-Store Unit, Hardware Prefetch, or core interactions).
- Drive block-level and core-level verification planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural behavior.
- Define verification strategies for instruction fetch, branch prediction, issue/dispatch, pipeline interactions, load/store ordering, memory consistency, and prefetch correctness.
- Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to expose corner cases and improve bug-finding efficiency.
- Partner early with architecture and design teams to review specifications, identify ambiguity, and improve design debugability and verification quality.
- Lead failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
- Contribute reusable methodology, infrastructure, and technical guidance to improve productivity and verification quality across core generations.
Requirements
Must-have technical skills and experience; preferred items listed separately.
- 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
- Hands-on experience with SystemVerilog and UVM-based verification.
- Direct CPU/core verification experience with a strong understanding of computer architecture and CPU microarchitecture.
- Experience in one or more high-performance CPU areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
- Strong verification flow methodology: test planning, constrained-random or directed stimulus generation, failure analysis, coverage analysis, and coverage closure.
- Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
Nice-to-have:
- Experience with out-of-order core verification.
- Experience using formal verification and/or emulation for high-risk or performance-sensitive verification problems.
- Experience collaborating with performance, compiler, system verification, and software teams.
- Mentoring experience and ability to influence verification methodology beyond immediate block/feature area.
- Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation.
Education Requirements
Bachelor's or Master's degree (BS/MS) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
