Staff Design Verification Engineer — High-Performance CPU Core

Job Title

Staff Design Verification Engineer — High-Performance CPU Core

Role Summary

Senior individual-contributor in the CPU Design Verification organization responsible for verification planning, execution, and quality for high-performance out-of-order CPU core blocks and core-level interactions.

Work with architecture, RTL, performance, and verification teams to identify risks early, define verification strategy, drive closure, and improve verification methodology across core generations.

Experience Level

Senior-level — requires substantial experience; posting specifies 7+ years of relevant ASIC/CPU/core/SoC verification experience.

Responsibilities

Lead verification activities for one or more high-performance CPU core areas and ensure signoff-quality verification.

• Own verification planning and execution for core areas such as Frontend, Midcore, Load-Store Unit, Hardware Prefetch, and related interactions.
• Drive block- and core-level verification planning, debug, coverage analysis, and coverage closure for complex CPU features.
• Define verification strategies for instruction fetch, branch prediction, issue/dispatch behavior, pipeline interactions, load/store ordering, memory consistency, and prefetch correctness.
• Develop and maintain verification environments: checkers, scoreboards, assertions, stimulus, and coverage models to expose corner cases.
• Partner with architecture and design teams early to review specs, identify ambiguities, and improve debugability and verification quality.
• Lead failure analysis and root-cause debug across specification, RTL, tests, and infrastructure.
• Contribute reusable methodology, infrastructure, and technical guidance to improve productivity across teams and future core generations.

Requirements

Must-have technical skills and verification experience. Preferred items are listed separately.

• Must-have: 7+ years of relevant ASIC/CPU/core/SoC design verification experience.
• Must-have: Hands-on experience with SystemVerilog and UVM-based verification.
• Must-have: Direct CPU/core verification experience and a strong understanding of computer architecture and microarchitecture.
• Must-have: Experience in one or more high-performance CPU areas (Frontend, Midcore, Load-Store Unit, memory ordering/consistency, hardware prefetch).
• Must-have: Solid verification flow methodology: test planning, constrained-random/directed stimulus, failure analysis, coverage analysis, and coverage closure.
• Must-have: Strong debug skills and ability to translate architectural intent into verification strategy and execution.
• Nice-to-have: Experience with out-of-order core verification.
• Nice-to-have: Experience using formal verification and/or emulation for high-risk or performance-sensitive verification problems.
• Nice-to-have: Experience collaborating with performance, compiler, system verification, and software teams.
• Nice-to-have: Mentoring experience and influence on verification methodology beyond a single block.
• Nice-to-have: Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (BS/MS in EE/CE/CS). Not specified whether equivalent experience is accepted.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.