Staff Design Verification Engineer – High Performance CPU Core

Job Title

Staff Design Verification Engineer – High Performance CPU Core

Role Summary

Senior individual-contributor role on SiFive's CPU Design Verification team focused on verification of high-performance out-of-order CPU core units. The engineer will define verification strategy, plan and execute block- and core-level verification, and raise verification quality across core features.

Experience Level

Senior — requires 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification.

Responsibilities

Accountable for verification planning, execution, and closure for complex CPU core features and interactions.

• Own verification planning and execution for one or more high-performance out-of-order CPU core areas (e.g., Frontend, Midcore, Load-Store Unit, Hardware Prefetch).
• Drive block- and core-level verification planning, debug, coverage analysis, and closure for complex microarchitectural behavior.
• Define verification strategies for instruction fetch, branch prediction, issue/dispatch, pipeline interactions, load/store ordering, hazard handling, memory consistency, and prefetch correctness.
• Develop and maintain verification environments: checkers, scoreboards, assertions, stimulus, and coverage models to expose corner cases.
• Partner with architecture and design teams early to review specifications, identify ambiguities, and improve debugability.
• Perform failure analysis and root-cause debug across specification, RTL, tests, and infrastructure.
• Contribute reusable methodology, infrastructure, and technical guidance to improve verification productivity and quality.

Requirements

Must-have technical skills and domain experience; preferred items listed separately.

• Must-have: 7+ years of relevant ASIC/CPU/SoC design verification experience.
• Must-have: Strong hands-on experience with SystemVerilog and UVM-based verification.
• Must-have: Direct CPU/core verification experience and solid understanding of computer architecture and microarchitecture.
• Must-have: Experience in one or more high-performance CPU areas (Frontend, Midcore, Load-Store Unit, memory ordering/consistency, hardware prefetch).
• Must-have: Familiarity with verification flow and methodology: test planning, constrained-random or directed stimulus, failure analysis, coverage analysis and closure.
• Must-have: Strong debug and root-cause analysis skills.
• Nice-to-have: Experience with out-of-order core verification, formal verification, or emulation for high-risk/performance-sensitive problems.
• Nice-to-have: Experience collaborating with performance, compiler, system verification, and software teams.
• Nice-to-have: Experience mentoring engineers and influencing verification methodology beyond an immediate block.
• Nice-to-have: Familiarity with scripting/programming for DV infrastructure (Python, C/C++).

Education Requirements

Bachelor's or Master's degree (BS/MS) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.