Staff Design Verification Engineer

Job Title

Staff Design Verification Engineer

Role Summary

Own verification strategy and execution for complex out-of-order (OOO) CPU cores and cache/memory subsystems, from ISA and micro-architecture through tape-out. Lead test-plan definition, verification implementation, coverage closure, and mentor junior verification engineers.

Work focuses on speculative execution, memory ordering, coherence, and end-to-end correctness for high-performance RISC-V based CPU designs. This role is based in Hyderabad and requires eligibility to work in India.

Experience Level

Senior; typically requires 8+ years in ASIC/SoC/IP design verification with substantial experience on out-of-order CPU or advanced core projects.

Responsibilities

Primary responsibilities include verification ownership, testbench architecture and implementation, formal/ assertion-based verification, debug, and methodology leadership.

• Define verification strategy and detailed test plans from ISA and micro-architecture specifications, emphasizing speculative execution, hazards, memory consistency, and coherence.
• Own verification for OOO core subsystems (front-end, back-end, ROB/retirement/recovery) and memory subsystem (LSU, TLBs, MMU, L1/L2 caches, coherence, fences, atomics).
• Architect and implement constrained-random, coverage-driven UVM environments, including generators, monitors, scoreboards, and protocol checkers.
• Develop reference models for ISA and memory model to enable end-to-end checking of retirement, architectural state, fences, and atomic semantics.
• Write and maintain assertions (SVA) and apply formal techniques to targeted units (ROB, scoreboard, arbiters, FIFOs, coherence controllers, TLB state machines).
• Lead debug of complex OOO bugs (ordering violations, rare hazards, coherence races, TLB edge cases) and work closely with RTL, micro-architecture, performance, SW, and post-silicon teams.
• Mentor junior DV engineers and evolve DV methodology, scenario libraries, and infrastructure to achieve coverage closure and sign-off criteria.

Requirements

Must-have:

• Strong expertise in SystemVerilog and UVM.
• Proven verification experience with out-of-order CPU micro-architecture (fetch, decode, rename, issue/scheduler, physical register files, bypass networks, ROB, flush/replay).
• Hands-on experience with load-store units, store buffers, speculative loads/stores, LR/SC/atomics, TLBs/MMU, and cache hierarchy/coherence protocols.
• Experience with coverage-driven verification, coverage closure, and large-scale regression environments.
• Assertion-based verification (SVA) skills and experience authoring assertions and checkers.
• Proven debugging skills and use of RTL debug tools to resolve complex, rare corner-case bugs.
• Ability to define verification strategies, lead cross-functional verification efforts, and mentor team members.

Nice-to-have:

• Experience verifying multi-core OOO systems and inter-core coherence.
• Experience applying formal verification to OOO structures (scoreboards, ROB, LSQs).
• Exposure to RISC-V or ARM ISA, privilege specs, virtualization, and security extensions.
• Experience with performance verification or micro-architectural modeling.
• Proven technical leadership on CPU or SoC tape-outs and methodology ownership.

Position requires successful background/reference checks and verification of right-to-work in India; offer may be contingent on export-control authorizations.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (explicitly listed in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.