Staff Design Verification Engineer – CPU Core Formal Verification

Job Title

Staff Design Verification Engineer – CPU Core Formal Verification

Role Summary

Staff individual-contributor in the CPU Design Verification organization responsible for planning and executing formal verification of high-performance out-of-order CPU core microarchitecture. Primary scope includes frontend, midcore control, issue/commit behavior, load-store interactions, clock-gating, and other high-risk or ordering-sensitive microarchitectural behaviors.

Experience Level

Senior - requires 7+ years of relevant ASIC/CPU/SoC design verification experience.

Responsibilities

Lead formal verification efforts for CPU core blocks and contribute reusable methodology and infrastructure.

• Own formal verification planning and execution from block-level proof strategy through closure and signoff.
• Define property-driven verification plans: assumptions, assertions, covers, abstractions, and closure criteria.
• Build and maintain scalable formal environments, property sets, checkers, harnesses, and proof infrastructure.
• Target high-value problems: pipeline control, issue/dispatch correctness, flush/replay, register/data movement, load-store ordering, hazards, forward progress, and clock-gating.
• Apply abstraction, decomposition, bounded proofs, connectivity checks, and other techniques to improve proof convergence.
• Analyze proof failures and counterexamples; drive fixes across RTL, properties, assumptions, and infrastructure.
• Collaborate with architecture, RTL, and simulation DV engineers to resolve ambiguities and align verification goals.
• Mentor engineers on property quality, formal-debug best practices, and verification methodology.

Requirements

Must-have skills and background for this role.

• Direct experience with CPU/core verification and solid understanding of computer architecture and microarchitecture.
• Hands-on formal verification experience for RTL: assertion-based verification, proof analysis, abstraction techniques, and closing non-trivial properties.
• Experience developing assertions and formal strategies for control-heavy, ordering-sensitive, or interface-sensitive hardware behavior.
• Strong debugging and root-cause skills across specification, RTL, properties, and verification infrastructure.
• Knowledge of verification methodology including test planning, failure analysis, coverage thinking, and signoff discipline.
• Familiarity with scripting/programming for automation and infrastructure (Python, Perl, Tcl, or similar).

Nice-to-have:

• Experience with out-of-order CPU core verification and applying formal methods to CPU-specific areas (issue logic, scoreboarding, LSU ordering, MMU/TLB, power/clock-gating).
• Experience with formal techniques for safety, liveness, deadlock, forward progress, connectivity, reset, and microarchitectural consistency checks.
• Experience improving formal convergence via abstraction, environment modeling, and assume-guarantee decomposition.
• Proven ability to mentor others and influence verification methodology beyond immediate scope.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.