Staff Design Verification Engineer - CPU Core Formal Verification

Job Title

Staff Design Verification Engineer - CPU Core Formal Verification

Role Summary

Staff individual-contributor within the CPU Design Verification organization. Lead formal verification for high-performance out-of-order CPU core microarchitecture, owning property-driven strategies, proof execution, failure analysis, and cross-team alignment.

Primary scope includes formal verification of frontend, mid-core control, issue/commit behavior, load-store interactions, clock-gating, and other ordering- or control-sensitive microarchitectural behaviors.

Experience Level

Senior - 7+ years of relevant ASIC, CPU/core, or SoC design verification experience.

Responsibilities

Plan and execute formal verification efforts for one or more CPU core areas through signoff-oriented closure.

• Define property-driven verification strategies: assumptions, assertions, covers, abstractions, and closure criteria.
• Create and maintain scalable formal environments, property sets, checkers, harnesses, and proof infrastructure.
• Target high-value problems: pipeline control, issue/dispatch correctness, flush/replay, register/data movement, load-store ordering, hazard handling, and clock-gating.
• Apply abstraction, decomposition, bounded proofs, connectivity checks, and X-propagation reasoning to improve convergence.
• Analyze proof failures and counterexamples; diagnose vacuity, over-constraint, and incompleteness; drive fixes in RTL, properties, or infrastructure.
• Collaborate with architecture, RTL, and simulation DV engineers to remove ambiguities and align verification results.
• Contribute reusable methodology, automation, and debug workflows across CPU programs.
• Mentor other engineers on property quality and formal-debug best practices.

Requirements

Must-have technical skills and experience for the role, followed by preferred qualifications.

• Must-have: 7+ years of relevant ASIC/CPU/SoC design verification experience with hands-on ownership of complex verification problems.
• Must-have: Direct experience with CPU/core verification and solid understanding of computer architecture and microarchitecture.
• Must-have: Strong hands-on formal verification experience for RTL: assertion-based verification, proof analysis, abstraction techniques, and closure of non-trivial properties.
• Must-have: Experience developing assertions and formal strategies for control-heavy, ordering-sensitive, or interface-sensitive hardware behavior.
• Must-have: Strong debugging and root-cause skills across specification, RTL, properties, and verification infrastructure.
• Must-have: Solid verification methodology knowledge including test planning, failure analysis, coverage thinking, and signoff discipline.
• Must-have: Familiarity with scripting or programming for automation (Python, Perl, Tcl, or similar).
• Nice-to-have: Experience with out-of-order CPU core verification and applying formal methods to frontend, issue logic, scoreboarding, commit, LSU ordering, MMU/TLB control, or power/clock-gating.
• Nice-to-have: Experience with formal techniques for safety, liveness, deadlock, forward progress, connectivity, reset, and microarchitectural consistency checks.
• Nice-to-have: Experience balancing formal and simulation approaches and improving formal convergence via abstraction and assume-guarantee decomposition.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (BS/MS in EE, CE, or CS) as stated in minimum qualifications.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.