Staff Design Verification Engineer – Coherent Interconnect

Job Title

Staff Design Verification Engineer — Coherent Interconnect

Role Summary

Staff-level individual contributor responsible for planning and driving verification of a next-generation cache-coherent interconnect subsystem with emphasis on CXL protocol behavior, bridge/adapter paths, and subsystem integration.

You will collaborate with architecture, RTL, formal, and software teams to define verification strategy, implement verification infrastructure, identify risks early, and raise verification quality across the interconnect effort.

Experience Level

Senior — typically 7+ years of ASIC/SoC design verification experience; this role expects independent ownership of complex block- or subsystem-level verification problems.

Responsibilities

Primary responsibilities include defining verification scope, building infrastructure, and driving closure of high-risk issues across interfaces and subsystem boundaries.

• Drive verification of subsystem behavior across protocol adaptation layers, bridge paths, and multiple interfaces with emphasis on CXL and coherent flows.
• Develop and maintain verification environments, checkers, scoreboards, assertions, constrained-random stimulus, and coverage models.
• Define directed and constrained-random scenarios to expose corner cases in coherency, ordering, arbitration, flow control, and QoS.
• Partner with architecture, RTL, formal, and software teams to clarify specifications and close ambiguities early.
• Analyze failures, isolate root cause across spec/RTL/testbench, and drive durable fixes.
• Deliver reusable methodology and automation that scale across the interconnect verification effort.
• Mentor and review work of other engineers to improve verification quality and practices across the team.

Requirements

Concise list of required and preferred skills for successful performance in this role.

• Must-have: 7+ years of hands-on ASIC or SoC design verification experience with ownership of complex block- or subsystem-level verification.
• Must-have: Strong protocol knowledge in CXL and at least one of CHI, ACE, AXI, or similar interconnect standards.
• Must-have: Proficient with SystemVerilog and UVM; experience building reusable verification infrastructure for complex hardware subsystems.
• Must-have: Deep understanding of cache-coherent systems, on-chip interconnects, memory-subsystem behavior, ordering and flow-control semantics, and related debug workflows.
• Must-have: Experience creating test plans, assertions, coverage models, scoreboards, and test content for complex subsystems.
• Must-have: Strong debugging and root-cause skills across specification, RTL, and testbench layers; strong scripting/automation skills (Python or similar).
• Must-have: Strong communication skills and experience collaborating across architecture, RTL, formal, and software teams.
• Nice-to-have: Experience with protocol-conversion or bridge-heavy subsystems, formal verification, performance-oriented verification, emulation or FPGA-assisted debug, and mentoring other engineers.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.