Staff Design Verification Engineer – Cache Verification

Job Title

Staff Design Verification Engineer – Cache Verification

Role Summary

Drive verification of cache and memory-subsystem functionality with emphasis on cache coherency, ordering, correctness, and subsystem integration for L2/L3 caches.

This is a staff-level individual-contributor role in the horizontal cache verification area, responsible for executing verification, building robust environments, debugging complex issues, and improving verification methodology across teams.

Experience Level

Senior (Staff). Requires 7+ years of ASIC, CPU, or SoC design verification experience.

Responsibilities

Key responsibilities include planning and executing cache verification and improving verification quality and reuse.

• Own verification planning and execution for L2/L3 cache and related cache-subsystem features, from block-level verification through subsystem integration.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for coherency, ordering, flow control, and error scenarios.
• Define and execute directed and constrained-random tests to expose corner cases in coherency, concurrency, backpressure, and integration behavior.
• Analyze failures, isolate root cause, and drive fixes across RTL, testbench infrastructure, assertions, and test content.
• Collaborate with architecture, design, and verification teams to clarify requirements and improve verification early in the development cycle.
• Write functional coverage, analyze coverage results, and close coverage holes to ensure verification completeness and signoff quality.
• Contribute reusable methodology, automation, and debug improvements that raise team-wide productivity and verification quality.

Requirements

Must-have technical skills and hands-on verification experience.

Must-have:

• 7+ years of experience in ASIC, CPU, or SoC design verification with ownership of complex verification problems at block or subsystem level.
• Strong expertise in SystemVerilog and UVM-based verification.
• Deep understanding of cache architecture, memory hierarchy, and cache coherency protocols/behavior.
• Experience building reusable testbenches, assertions, checkers, scoreboards, coverage models, and debug infrastructure.
• Strong debugging skills with ability to root-cause issues across specification, RTL, and testbench layers.
• Experience with coverage analysis and closure, constrained-random verification, and metrics-driven signoff.
• Solid understanding of computer architecture and microarchitecture fundamentals.

Nice-to-have:

• Direct experience verifying multiple cache levels, including private and shared cache structures.
• Experience with memory consistency, weak ordering, and multicore verification challenges.
• Experience with performance-oriented verification, formal techniques, or emulation/FPGA-assisted debug.
• Familiarity with Python, C/C++, or scripting languages used for DV infrastructure and automation.
• Ability to influence technical direction across architecture, design, and verification teams.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.