Staff Design Verification Engineer - Cache Verification

Job Title

Staff Design Verification Engineer - Cache Verification

Role Summary

Senior individual-contributor responsible for planning and executing verification for L2/L3 cache and memory-subsystem features, with emphasis on cache coherency, ordering, and subsystem integration. Works across architecture, design, and verification teams to ensure correctness from block level through subsystem signoff.

Experience Level

Senior — typically 7+ years of ASIC/CPU/SoC design verification experience.

Responsibilities

Accountable for verification strategy, implementation, and closure for cache and related subsystems.

• Own verification planning and execution for L2/L3 cache and related subsystem features, from block-level verification through subsystem integration.
• Develop and maintain testbenches, checkers, scoreboards, assertions, stimulus, and coverage models for coherency, ordering, flow control, and error scenarios.
• Create directed and constrained-random tests to expose corner cases in coherency, concurrency, backpressure, and integration behavior.
• Analyze failures, isolate root causes, and drive fixes across RTL, testbench infrastructure, and test content.
• Collaborate with architecture and design teams to clarify requirements and improve verification quality early in the cycle.
• Write and analyze functional coverage and close coverage holes to reach signoff criteria.
• Contribute reusable methodology, automation, and debug improvements to raise team productivity.

Requirements

Key technical skills and experience required and preferred for the role.

• Must-have: 7+ years of hands-on ASIC, CPU, or SoC design verification with ownership of complex block or subsystem verification.
• Must-have: Strong expertise in SystemVerilog and UVM-based verification.
• Must-have: Deep understanding of cache architecture, memory hierarchy, and cache coherency protocols/behavior.
• Must-have: Experience building reusable testbenches, assertions, checkers, scoreboards, coverage models, and debug infrastructure.
• Must-have: Strong debugging and root-cause analysis skills across specification, RTL, and testbench layers.
• Must-have: Experience with coverage analysis and closure, constrained-random verification, and metrics-driven signoff.
• Must-have: Solid understanding of computer architecture and microarchitecture fundamentals.
• Nice-to-have: Experience verifying multiple cache levels (private and shared), memory consistency/weak ordering, multicore verification challenges.
• Nice-to-have: Performance-oriented verification, formal techniques, or emulation/FPGA-assisted debug experience.
• Nice-to-have: Familiarity with Python, C/C++, or scripting for DV infrastructure and automation; ability to influence cross-team technical direction.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.