Staff Design Verification Engineer

Job Title

Staff Design Verification Engineer

Role Summary

Lead pre-silicon verification for complex SoC and subsystem designs, define verification architecture and drive verification from planning to closure. Work within a multifunctional engineering team and coordinate with emulation, FPGA, firmware and design teams to ensure end-to-end system correctness.

This role focuses on scalable DV methodology, UVM-based testbench architecture, coverage closure, and applying formal, emulation and power-aware techniques to deliver high-quality silicon.

Experience Level

Senior level. The role expects an experienced verification engineer; the original posting indicates a guideline of 8+ years of experience.

Responsibilities

Primary responsibilities include ownership of pre-silicon verification for large integrated products and driving verification methodology improvements.

• Lead verification planning, architecture, execution and closure for SoC or subsystem designs.
• Architect and implement UVM-based testbenches and scalable DV flows.
• Define and execute test plans; drive functional and code coverage closure at block and subsystem levels.
• Verify microprocessor-based systems, AI/ML accelerators and high-speed peripherals.
• Collaborate with emulation, FPGA and firmware teams for end-to-end system validation.
• Apply formal verification techniques for IP and subsystem validation.
• Lead NoC/interconnect verification and coverage optimization.
• Perform system-level use-case validation including performance verification and analysis.
• Develop and validate end-to-end scenarios and drive verification to meet schedule and quality targets.

Requirements

Key technical skills and experience required or strongly preferred.

• Must-have: Strong hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven experience in verification closure using functional and code coverage metrics at block and subsystem levels.
• Expertise in NoC, bus and interconnect verification, including coverage analysis and optimization.
• Experience architecting testbench environments and implementing scalable DV flows and methodologies.
• Hands-on experience in power-aware verification using UPF, including power analysis and optimization.
• Exposure to formal verification, including flow setup and connectivity/functional checks.
• Familiarity with gate-level simulations (GLS) with timing annotation.
• Proficiency in C/C++, SystemC and scripting (Python/Tcl/Shell).
• Excellent communication and collaboration skills; ability to work across global teams.
• Nice-to-have: Familiarity with processor ecosystems (ARM, RISC-V, Tensilica) and AI/ML or GPU-based architectures.

Education Requirements

B.Tech or M.Tech degree (as stated in the original posting). The posting pairs this education expectation with the experience guideline of 8+ years.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.