Staff Design Verification Engineer

Job Title

Staff Design Verification Engineer

Role Summary

Lead verification of complex out-of-order (OOO) CPU cores and memory subsystems. Own verification strategy, methodology, execution, coverage closure, and sign-off for major core blocks while providing technical leadership and mentoring within the design verification (DV) team.

Experience Level

Senior — typically 8+ years of hands-on ASIC/SoC/IP design verification experience.

Responsibilities

Key responsibilities include technical ownership of verification, testbench and methodology leadership, coverage and sign-off, debugging, and mentoring.

• Own verification for major OOO core subsystems (front-end, rename/register mapping, issue queues/schedulers, execution units, ROB/retire, exceptions, LSU, caches/TLBs/MMU and coherence interfaces).
• Translate ISA and micro-architecture specifications into detailed verification plans and test strategies.
• Architect and implement SystemVerilog/UVM testbenches: reusable environments, agents, monitors, scoreboards, and reference models.
• Develop constrained-random and targeted stimulus, and scenario libraries for speculation, memory ordering, and multi-core interactions.
• Define and evolve DV methodology and reuse patterns; contribute to common DV infrastructure across IPs and projects.
• Define coverage models (functional, code, assertion, scenario) and drive coverage closure and sign-off for owned blocks.
• Develop and maintain SVA assertion sets for OOO properties and verify memory-model compliance.
• Lead debug of complex OOO failures and collaborate with micro-architecture, RTL, performance/modeling, and post-silicon teams.
• Mentor junior and mid-level DV engineers; lead DV design reviews and contribute verification perspective to architecture reviews.

Requirements

Must-have skills and experience.

• 8+ years of hands-on ASIC/SoC/IP design verification experience.
• Significant experience verifying out-of-order or superscalar CPU cores or similarly complex execution pipelines.
• Strong proficiency in SystemVerilog and UVM (or equivalent class-based methodology).
• Deep understanding of CPU micro-architecture: front-end, rename/physical register files, dependency tracking, schedulers/issue queues, ROB/commit logic, exception/interrupt/flush paths, LSU/store buffer, speculative loads/stores, atomics/fences, and cache/TLB/MMU/coherence interfaces.
• Experience with constrained-random, coverage-driven verification and writing/debugging SVA assertions.
• Experience with major simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
• Strong problem-solving and debug skills for complex concurrency and ordering issues; proven ability to drive technical topics across teams to completion.
• Clear written and verbal communication skills and experience presenting designs, plans, and status to technical and non-technical stakeholders.
• Authorized to work in India; employment subject to background/reference checks and export-control authorization as required.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.