Staff Design for Test (DFT) / STA Engineer

Job Title

Staff Design for Test (DFT) / STA Engineer

Role Summary

Technical leader responsible for DFT architecture, implementation, and static timing analysis (STA) sign-off for high-performance multi-core SoCs. Own the DFT methodology, timing constraints, and STA sign-off across test modes while collaborating with RTL, Physical Design, and Product Engineering teams to enable first-pass silicon success.

Experience Level

Senior-level engineering role. Specific level will be confirmed during interview; candidates with substantial DFT and STA experience for complex SoCs are expected.

Responsibilities

Key responsibilities include:

• Define and implement full DFT methodology for high-speed, multi-core designs, including scan insertion and memory BIST strategies.
• Lead generation and validation of DFT timing constraints (SDC) for all test modes (Scan, JTAG, Memory BIST) and own STA timing sign-off at block and top level.
• Develop and maintain timing sign-off flows and sign-off criteria for multiple test modes and corners using industry STA tools.
• Work with RTL, synthesis, and P&R teams to resolve timing violations and produce timing ECOs to achieve closure.
• Coordinate DFT requirements across SOC, IP, and product teams throughout RTL insertion, synthesis, P&R, and STA stages.
• Participate in ATE test pattern targeting, silicon validation, and debug activities with test and product engineering.
• Propose and implement improvements to DFT and STA flows to increase robustness and efficiency.

Requirements

Must-have technical skills and experience:

• Deep expertise in Design for Test concepts: scan compression/insertion, memory BIST and repair, JTAG/IJTAG, and at-speed test methodologies.
• Strong STA skills: timing modes, constraints, corners, and sign-off for complex SoCs; experience with tools such as Synopsys PrimeTime or Cadence Tempus.
• Experience with DFT-specific timing modes (scan shift, slow/fast capture, JTAG, Memory BIST) and creating/validating SDC for those modes.
• Proficiency in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.
• Solid understanding of clock domain crossings (CDC), reset domain crossings (RDC), and multi-mode timing sign-off strategies.
• Proven ability to collaborate cross-functionally with RTL, Physical Design (synthesis, P&R), and product/test engineering teams.
• Experience debugging silicon and supporting characterization/validation activities.
• Employment may be contingent on eligibility to access U.S. export-controlled technology; offers may require U.S. citizenship, permanent residency, or prior license approval.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.