Staff Design for Test (DFT) Engineer

Job Title

Staff Design for Test (DFT) Engineer

Role Summary

Senior DFT engineer responsible for designing and implementing test architecture and flows for complex mixed-signal/ASIC/SoC products. The role covers DFT specification, automation of DFT flows, ATPG pattern delivery, and silicon bring-up support.

Works across product teams to achieve high test coverage, low power and short test time; provides methodology support and mentors junior engineers.

Experience Level

Senior — requires substantial experience. The posting specifies 10+ years of directly related ASIC/SoC DFT experience.

Responsibilities

Primary responsibilities include DFT architecture, implementation, verification, and support for silicon test and production.

• Define DFT specifications and architecture for ASIC/SoC projects.
• Implement scan insertion, compression insertion, on-chip clock control insertion, and related DFT features.
• Develop and maintain DFT flow automation and methodology improvements.
• Generate and verify ATPG patterns to meet coverage and test-time targets.
• Perform pre- and post-silicon verification and debug; support silicon bring-up and failure analysis.
• Provide gate-level simulation with SDF and DFT verification.
• Mentor and train junior DFT engineers and collaborate with peer teams.

Requirements

Must-have skills and experience are listed first; preferred skills follow.

Must-have

• 10+ years of ASIC/SoC DFT experience.
• Expert knowledge of DFT architecture, planning, and implementation.
• Hands-on experience with Tessent DFT tools.
• Expertise in Scan, Test Compression, At-Speed Test, MBIST, and LBIST.
• Hands-on experience with ATPG, scan insertion, compression insertion, and on-chip clock control insertion.
• Gate-level simulation using SDF and experience supporting silicon bring-up and failure analysis/debug.
• Scripting experience (Perl, Python, Tcl).
• Strong verbal and written communication; ability to work with cross-functional teams.

Preferred

• Experience with Cadence and Synopsys DFT toolchains.
• Familiarity with IEEE 1149/JTAG and Static Timing Analysis.
• Experience with additional BIST approaches, synthesis and DFT insertion workflows, and low-power scan/UPF.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.