Staff CPU/NPU Architecture RTL Design Engineer

Job Title

Staff CPU/NPU Architecture RTL Design Engineer

Role Summary

Design RTL and micro-architectural blocks for high-performance CPU and AI (NPU) processors used in Snapdragon platforms. Work with a cross-functional ASIC team to deliver energy-efficient processor IP focused on inference and general-purpose compute.

Experience Level

Senior (Staff level). This is a senior engineering role requiring substantial hands-on ASIC/RTL experience; see Education Requirements for degree and years guidance.

Responsibilities

Primary engineering responsibilities include:

• Architect, micro-architect, and implement RTL for CPU and NPU subsystems.
• Write and review high-quality RTL code and scripts to meet performance, area, and power targets.
• Design and optimize datapaths (fixed-point and floating-point) and computer-arithmetic units.
• Implement instruction fetch, scheduling, register renaming, branch prediction, out-of-order execution, and dispatch/scheduler logic.
• Design memory sub-systems: load/store, caches, coherence, atomics, and consistency protocols.
• Collaborate with verification, validation, integration, power, and circuit-design teams to bring IP to silicon.
• Profile and apply PPA (power, performance, area) optimizations; participate in design tradeoffs.
• Support debug architecture and system-level integration for multi-core / multi-threaded processors.

Requirements

Technical must-haves and preferred skills. Degree and formal years-of-experience are listed in Education Requirements below.

• Must-have: Strong RTL design and coding skills for high-performance processors.
• Must-have: Deep understanding of CPU/NPU micro-architecture and processor subsystems.
• Must-have: Experience with computer arithmetic and datapath design (fixed/floating point).
• Must-have: Knowledge of instruction fetch, scheduling, register renaming, branch prediction, and out-of-order mechanisms.
• Must-have: Expertise in memory subsystems, load/store paths, caches, coherence, and consistency.
• Must-have: Familiarity with RISC-V or comparable ISA concepts.
• Nice-to-have: Experience with matrix-multiply engines, vector extensions, and accelerator integration.
• Nice-to-have: Background in multi-processor/multi-threaded system design, power-management, and circuit-level considerations.

Education Requirements

Required: Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or related field with 3+ years of related experience; OR PhD in Science, Engineering, or related field with 2+ years of related experience. Equivalent practical experience in ASIC/RTL design may be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.