Staff CPU/NPU Architecture RTL Design Engineer
QualcommJob Title
Staff CPU/NPU Architecture RTL Design Engineer
Role Summary
Design and implement RTL for high-performance, energy-efficient CPU and NPU IP used in Snapdragon processors and AI inference engines. Work on micro-architecture, RTL coding, verification handoff, and PPA optimization within the Hexagon NPU team in Markham.
Experience Level
Senior level. The posting indicates experienced engineers are sought and mentions an ideal baseline of 2+ years; minimum experience expectations vary by degree (see Education Requirements).
Responsibilities
Primary responsibilities include architecting and delivering CPU/NPU RTL, optimizing for power/performance/area, and collaborating across design, verification, and integration teams.
- Specify and implement RTL micro-architecture for CPU/NPU blocks.
- Write and maintain RTL code and associated design documentation.
- Perform micro-architecture tradeoffs focusing on PPA (power, performance, area).
- Design and optimize datapaths (fixed/floating point, matrix multiply, vector units).
- Work on memory subsystem features: load/store, caches, coherence, atomics.
- Contribute to branch prediction, out-of-order execution, dispatch, and scheduling logic.
- Debug architecture and participate in integration/bring-up with verification teams.
- Collaborate with circuit and power teams to meet system-level goals.
Requirements
Technical must-haves and preferred skills. Degree and minimum years are listed under Education Requirements.
- Must-have: Strong knowledge of CPU/AI processor micro-architecture and RTL design; proven RTL coding experience for high-performance processors.
- Must-have: Experience with computer arithmetic, instruction fetch, register renaming, scheduling, and out-of-order pipelines.
- Must-have: Experience with memory subsystems, load/store units, caches, coherence, and atomics.
- Must-have: Familiarity with performance optimization and PPA tradeoffs for ASICs.
- Nice-to-have: Experience with matrix multiply engines, vector extensions, RISC-V, multi-threaded/multi-processor systems.
- Nice-to-have: Background in power-management or circuit-level design and debug of processor subsystems.
Education Requirements
One of the following is required: Bachelor's degree in Science, Engineering, or a related field plus 4+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or a related field plus 3+ years of relevant experience; OR PhD in Science, Engineering, or a related field plus 2+ years of relevant experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
