Staff CPU Design Verification Engineer

Job Title

Staff CPU Design Verification Engineer

Role Summary

Lead verification strategy and execution for out-of-order (OOO) CPU cores and cache/memory subsystems. Work with architecture, RTL, software, and post-silicon teams to define testplans, drive coverage closure, and sign off speculative execution, memory ordering, and coherence behavior through tape-out.

Experience Level

Senior - typically 8+ years in ASIC/SoC/IP design verification, with significant experience on OOO CPU or advanced core projects.

Responsibilities

Primary responsibilities include ownership of verification for OOO core and memory subsystems, building scalable testbenches, applying assertions and formal techniques to targeted units, and mentoring junior engineers.

• Define verification strategy and create testplans from ISA and micro-architecture specs, focusing on speculative execution, hazards, memory ordering, and coherence.
• Own verification of OOO subsystems: front-end (fetch, branch prediction, decode), back-end (issue queues, execution, bypass), retirement/ROB, and LSU/TLB/MMU/cache hierarchy.
• Architect and implement constrained-random, coverage-driven UVM testbenches, scoreboards, monitors, and reusable generators for OOO stress scenarios.
• Drive coverage closure across functional, code, assertion, and scenario coverage to sign-off criteria.
• Write and maintain assertions (SVA) for key OOO properties and apply formal methods to targeted units where appropriate.
• Lead debug of complex corner-case bugs (ordering violations, speculation issues, coherence races, TLB edge cases) and coordinate root-cause analysis with cross-functional teams.
• Improve DV methodology and infrastructure: scenario libraries, memory-model checkers, and large-scale regression environments.
• Mentor and provide technical leadership to junior DV engineers; collaborate across architecture, design, SW, and post-silicon teams.

Requirements

Must-have technical skills and practical experience for day-one impact.

• Strong SystemVerilog and UVM expertise; hands-on experience building and running large regression suites.
• Direct verification experience with OOO CPU micro-architecture (fetch/decode/rename, issue/scheduler, physical register files, ROB, flush/replay, exceptions/interrupts).
• Experience with memory subsystem verification: LSU, load/store ordering, store buffer, TLBs, MMU, caches, coherence protocols, and fence/atomic semantics.
• Solid understanding of memory consistency models (e.g. RVWMO, TSO) and how they map to hardware.
• Assertion-based verification (SVA) and coverage-driven methodologies; experience driving coverage closure to sign-off.
• Proven debugging skills and familiarity with debug tools for isolating rare/complex RTL bugs.

Nice-to-have

• Experience with formal verification on OOO structures (ROB, scoreboard, LSQs) and multi-core coherence validation.
• Exposure to RISC-V or ARM ISA, privilege/virtualization extensions, or performance verification and micro-architectural modeling.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (as stated in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.