Staff CAD Engineer (Silicon)

Job Title

Staff CAD Engineer (Silicon)

Role Summary

The Staff CAD Engineer will develop flows, methodologies and algorithms to improve power, performance and area (PPA) for state-of-the-art GPU cores. The role sits on the Graphics team and works closely with microarchitecture, implementation, power, sign-off and post-silicon teams to drive PPA improvements and deliver designs from RTL to GDSII.

Experience Level

Senior (Staff) level. Preferred 5–7 years developing PPA methodologies; minimum qualifications provide 2–4+ years of ASIC-related experience depending on degree. Equivalent practical experience will be considered.

Responsibilities

Key responsibilities include:

• Develop and implement CAD flows, methodologies and algorithms to improve PPA for GPU cores.
• Collaborate with graphics microarchitecture, implementation, power, sign-off and post-silicon teams to integrate improvements.
• Support delivery of GPU cores through the ASIC flow from RTL to GDSII, including synthesis, timing closure and physical implementation considerations.
• Define and manage design constraints for power, timing, clocking and interfaces.
• Perform formal verification checks, RTL-to-netlist and netlist-to-netlist validation, and assist with sign-off activities.
• Perform clock tree analysis, optimization and ECO generation for functional and timing fixes.
• Identify flow and process improvements and implement automation to increase delivery quality and efficiency.
• Work independently and contribute to cross-functional problem solving and design trade-offs.

Requirements

Must-have technical skills and experience (education listed separately):

• (Must) Practical experience with RTL and basic digital design flows, and familiarity with ASIC design flow from synthesis to GDS.
• (Must) Knowledge of RTL synthesis and physically aware synthesis tools, static timing analysis and timing closure techniques.
• (Must) Familiarity with Verilog/SystemVerilog and formal verification concepts.
• (Must) Experience with ECO methods, clock tree analysis/optimization, and managing PPA trade-offs.
• (Must) Scripting and automation skills (UNIX shell, Python, Perl and/or TCL).
• (Nice-to-have) Hands-on experience with EDA tools such as Synopsys Fusion Compiler, RTL-Architect, PrimePower, PrimeTime and Prime Closure.
• (Nice-to-have) Prior experience delivering GPU or complex ASIC blocks from RTL to GDSII and semi-custom flow development.
• Strong analytical, interpersonal skills and the ability to work independently and as part of a team.

Education Requirements

Required: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering or related Science/Engineering field (or equivalent practical experience). Preferred: Master’s in Computer Engineering, Computer Science or Electrical Engineering. PhD holders also acceptable. Degree-to-experience mapping specified in source: Bachelor’s +4 years, Master’s +3 years, PhD +2 years of ASIC design/verification/validation/integration experience; equivalent experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.