Staff CAD Engineer (PSI)

Job Title

Staff CAD Engineer (PSI)

Role Summary

You will join Marvell's Central CAD and Design Services (CCDS) — the PSI CAD team responsible for power, signal and integrity signoff methodology across Marvell's business units. The role focuses on developing and maintaining IR/EM and dynamic IR analysis flows for block- and full-chip signoff, supporting tapeout activities, and interfacing with EDA vendors.

Primary tasks are engineering-focused: flow development, automation, signoff closure, documentation, and knowledge transfer for advanced-node ASIC/SoC projects.

Experience Level

Senior — typically requires 6+ years of relevant industry experience in PSI/IR/EM signoff and production ASIC/SoC flows.

Responsibilities

The role's primary duties include developing signoff methodology, executing analyses, automating flows, and supporting tapeouts.

• Develop and maintain block-level and full-chip static IR/EM analysis flows and methodology.
• Develop and validate dynamic IR analysis (vectorless and vector-based using VCD/FSDB) with and without package models.
• Configure and tune Out-of-Context (OOC) and In-Context block-level IR analysis.
• Perform Early Rail / left-shifted IR analyses at floorplan stages to detect power-grid weaknesses.
• Integrate package-aware IR simulation and chip power model generation into signoff flows.
• Interface with EDA vendors to evaluate features, report issues, and drive tool improvements.
• Develop automation and debug scripts (Tcl, Python) to streamline flow execution and reporting.
• Support tapeout activities to ensure IR/EM signoff closure across blocks and full-chip designs.
• Document methodology and provide training and knowledge transfer to global teams.

Requirements

Must-have and preferred qualifications for successful candidates.

• Must-have: 6+ years hands-on experience with Cadence Voltus for IR drop and EM analysis in production ASIC/SoC flows.
• Must-have: Proven experience running block-level and full-chip PSI signoff on advanced technology nodes (7nm, 5nm, or 3nm).
• Must-have: Strong understanding of static and dynamic IR analysis flow and methodology, including hierarchical approaches.
• Must-have: Knowledge of DC and AC-EM analysis and their impact on designs.
• Must-have: Experience with package-aware IR simulation and chip power model generation.
• Preferred: Experience with thermal flows and multi-die IR/EM analysis.
• Preferred: Strong scripting skills (Tcl, Python) for automation of flows and reporting.
• Other: Eligible to access export-controlled technology; candidates may be subject to export license review.
• Interview note: Use of AI tools during interviews is prohibited and may disqualify candidates.

Education Requirements

B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.