Staff CAD Engineer (Power Signal Integrity)

Job Title

Staff CAD Engineer (Power Signal Integrity)

Role Summary

This role is part of Marvell's Central CAD and Design Services (CCDS) organization, within the CAD Power & Signal Integrity (PSI) team. The team defines and maintains PSI signoff methodology and flows used across Marvell's business units.

The engineer will develop and maintain IR/EM analysis flows and methodologies, support tapeout signoff, collaborate with EDA vendors, and provide automation and training to design teams.

Experience Level

Senior (Staff) - typically 5+ years of relevant ASIC/SoC PSI/CAD experience; the posting specifies 5+ years.

Responsibilities

Main technical responsibilities and deliverables for the role.

• Develop and maintain block-level and full-chip static IR/EM analysis flows and methodology for signoff.
• Develop and validate dynamic IR analysis approaches (vectorless and vector-based using VCD/FSDB) at block and full-chip levels, with and without package models.
• Implement and tune Out-of-Context (OOC) and In-Context block-level IR analysis flows.
• Perform early rail/left-shifted IR analysis (e.g., Early Rail Analysis) to detect power-grid issues at the floorplan stage.
• Interface with EDA vendors: evaluate tool features, report defects, and drive improvements in tools and methodology.
• Develop automation and debug scripts (Tcl, Python) to streamline flow execution and reporting.
• Support tapeout activities and ensure IR/EM signoff closure across blocks and full-chip designs.
• Document flows, share knowledge, and provide training to global teams.

Requirements

Must-have technical skills and constraints; followed by a short list of preferred skills.

• 5+ years hands-on experience with Cadence Voltus for IR drop and EM analysis in production ASIC/SoC flows.
• Proven experience driving block-level and full-chip PSI signoff on advanced process nodes (7nm, 5nm, or 3nm).
• Strong understanding of static and dynamic IR analysis flow and methodology, including hierarchical approaches.
• Good understanding of DC and AC-EM analysis and its implications on reliability and signoff.
• Familiarity with package-aware IR simulation and chip power-model generation flows.
• Ability to write and maintain automation scripts (Tcl, Python) to support flows and reporting.
• Eligibility to access export-controlled technology and data; candidates may be subject to export license review prior to employment.
• Excellent debugging, documentation, and collaboration skills across distributed teams.

Nice-to-have:

• Experience with thermal analysis flows.
• Experience with multi-die IR/EM analysis.

Education Requirements

B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field (as stated in the posting).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.