Staff ASIC STA Engineer

Job Title

Staff ASIC STA Engineer

Role Summary

Lead ASIC static timing analysis (STA) and timing closure efforts for Tensordyne's multimodal generative AI inference ASICs. Act as a hands-on individual-contributor technical lead responsible for full-chip timing signoff, STA workflow development, and improving block- and chip-level timing methodologies.

Experience Level

Senior - 10+ years of hands-on ASIC engineering experience with VLSI/SoC physical design and STA.

Responsibilities

Own and improve timing analysis and STA workflows across block and full-chip scopes, and support other ASIC engineers in timing closure.

• Lead development and maintenance of hierarchical STA, timing analysis, and clock-analysis flows for full-chip signoff.
• Create and validate SDC constraints and timing models for high-speed IP (PCIe, SerDes) and multi-clock domain blocks.
• Drive timing closure, signoff activities, and timing ECO generation at both block and chip level.
• Collaborate with backend physical-design engineers on clock trees, routing impacts, and ECO implementation.
• Design, implement, and optimize EDA workflows using vendor tools and internal automation to scale ASIC STA processes.
• Guide and mentor engineering colleagues on STA best practices and troubleshooting complex timing issues.

Requirements

Must-have skills and experience required for immediate contribution.

• 10+ years of ASIC engineering experience focused on physical design and STA.
• Deep knowledge of STA methodologies and hierarchical timing analysis.
• Hands-on experience with signoff tools such as Synopsys PrimeTime or Cadence Tempus.
• Proven ability to write and validate SDC constraints for high-speed interfaces (PCIe, SerDes) and multi-clock domains.
• Experience owning full-chip timing closure, generating timing ECOs, and coordinating signoff flows without direct reports.
• Familiarity with backend tools and flows (place-and-route) and understanding clock-tree and routing impacts on timing.
• Strong analytical and communication skills for cross-functional collaboration in a global engineering team.

Nice-to-have:

• Experience with Genus/Innovus or equivalent RTL-to-GDS flows as they relate to STA.
• Experience developing or improving internal EDA automation and scalable timing workflows.
• Interest or prior exposure to generative AI accelerator architectures.

Education Requirements

Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.

About the Company

Company: Tensordyne

Tensordyne is a startup developing high-performance, low-power AI inference processors and multi-chip systems for generative AI acceleration in data centers. The company focuses on ASIC design, verification, and integration of computational accelerators with third-party SoC IP.