Staff ASIC RTL Design (Turing) - Engineer
QualcommJob Title
Staff ASIC RTL Design (Turing) - Engineer
Role Summary
Senior RTL/ASIC engineer on the Turing team responsible for microarchitecture, RTL implementation, and subsystem integration for high-performance AI/ML SoCs. Works within Qualcomm's Hardware Engineering organization and partners with product, verification, synthesis, power, and DFT teams to meet performance, power, area, and schedule targets.
Experience Level
Senior - requires significant experience; the posting specifies 8+ years of relevant experience.
Responsibilities
You will lead or contribute to RTL design and subsystem integration to meet PPAS goals and delivery milestones.
- Collaborate with product definition and architecture teams to translate requirements into microarchitecture and RTL plans.
- Define block-level design (diagrams, interfaces, clocking, transaction flow, pipelines, low-power strategies).
- Implement and review RTL (Verilog/SystemVerilog); develop microarchitecture and coding strategies.
- Lead or mentor engineers on RTL coding, function/performance simulation, and debug.
- Drive static checks and verification flows (Lint, CDC, FV) and manage UPF/low-power flows.
- Develop assertions and white-box test coverage for design verification.
- Produce and deliver key design collateral (timing constraints, UPF, performance specifications).
- Coordinate with power, synthesis, DFT, and PD teams on use cases, dynamic power, and datapath implications.
Requirements
Must-have technical skills and experience (degree details are in Education Requirements below).
- 8+ years of experience in ASIC/RTL design or related hardware engineering roles.
- Strong knowledge of Verilog/SystemVerilog, simulators, and waveform debugging tools.
- Understanding of computer system architecture and AI/ML accelerator design.
- Experience with high-performance design techniques and microarchitecture trade-offs.
- Familiarity with NoC design principles and performance budgeting (bandwidth, latency).
- Experience defining bus/transaction sizing across voltage/frequency corners.
- Practical experience interacting with power and synthesis teams on use cases and dynamic power.
- Knowledge of logic design principles with timing and power implications; experience with SOC DFT and PD collateral exchanges.
- Ability to lead technical discussions and drive design quality across stakeholders.
Education Requirements
Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field. Posting specifies degree plus experience alternatives: Bachelor's + 3+ years, Master’s + 2+ years, or PhD + 1+ year in hardware engineering or related work.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
