Staff ASIC Digital Verification Design Engineer
Senior verification engineer responsible for developing verification environments and validating complex ASIC Interface IP. You will work on functional verification, coverage closure, and collaborate with design and architecture teams to deliver reliable IP.
You will join a verification team focused on Interface IP protocols and verification methodology improvements.
Senior β the role is at staff/senior level. The posting requests 5+ years of ASIC digital verification experience.
Primary responsibilities include planning and executing verification for Interface IP and mentoring junior engineers.
Must-have technical skills and experience.
Bachelor of Science in Electrical Engineering (BSEE) or Master of Science in Electrical Engineering (MSEE) specified.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
