Staff ASIC Design Verification Engineer
SynopsysJob Title
Staff ASIC Design Verification Engineer
Role Summary
The Staff ASIC Design Verification Engineer will develop and execute verification plans for high-bandwidth memory (HBM) related ASIC IP and test-chips. You will work within a mixed-signal design and verification team to verify RTL at block and chip level, improve test coverage, and debug complex system failures.
The team focuses on high-performance, low-power silicon IP; this role supports specification-to-test activities and helps reduce product risk and time-to-market.
Experience Level
Senior (Staff). The posting specifies a minimum of 2+ years of digital design/verification experience; the role assumes senior-level responsibility within the verification team.
Responsibilities
Primary responsibilities include planning and executing verification activities and diagnosing complex failures.
- Verify ASIC RTL at chip and block levels.
- Define, document, and track verification test plans.
- Design and implement constrained-random SystemVerilog testbenches using UVM.
- Create and analyze functional coverage and perform code/coverage analysis.
- Write and maintain SystemVerilog assertions.
- Debug firmware, RTL, and gate-level simulation failures.
- Report and track bugs using tools such as Jira.
Requirements
Must-have technical skills and professional traits are listed first; followed by concise nice-to-have items.
- Must-have: Experience writing testcases and testbenches in SystemVerilog and UVM.
- Proven ability to debug complex testbench and design-related issues across RTL, gate, and firmware domains.
- Solid understanding of digital circuit design and verification methodologies.
- Familiarity with scripting (Python or Perl) for testbench automation and data processing.
- Experience with bug-tracking tools (e.g., Jira) and code/coverage analysis workflows.
- Self-motivated, organized, and able to communicate effectively with cross-functional teams.
Nice-to-have: Prior work on HBM or similar high-performance memory IP; mixed-signal verification experience; experience with gate-level simulation flows.
Education Requirements
Bachelor of Science in Electrical Engineering (BSEE) or Master of Science in Electrical Engineering (MSEE) is specified by the employer, with a minimum of 2+ years of digital design/verification experience.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
