Staff Applications Engineer - ASIC Physical Design (TCL/Python)

Job Title

Staff Applications Engineer - ASIC Physical Design (TCL / Python)

Role Summary

Provide hands-on technical support and implementation guidance to customers using Synopsys physical-design tools, with emphasis on Fusion Compiler and the RTL-to-GDS flow. Work with customer design teams and internal R&D to reproduce issues, deliver solutions, and improve tool behavior for advanced-node designs.

This role focuses on debugging place-and-route, timing closure, congestion, power optimization, and automation to help customers meet tapeout schedules and quality goals.

Experience Level

Senior-level. The posting requests at least 5 years of hands-on ASIC, physical design, implementation, or CAD engineering experience.

Responsibilities

Primary responsibilities include customer support, design debug, automation, and collaboration with product teams.

• Support customers through physical design implementation and design closure using Synopsys tools.
• Debug timing, power, area, congestion, routing, and runtime optimization issues across the RTL-to-GDS flow.
• Provide technical guidance on synthesis, place-and-route, timing closure, and power optimization methodologies.
• Build and maintain automation scripts (TCL) and use Python to streamline workflows and accelerate turnarounds.
• Leverage AI-assisted tools and automation to improve productivity and accelerate issue resolution.
• Collaborate with internal R&D to reproduce customer issues and feed real-world cases into product development.
• Present technical recommendations to senior customer engineers and design leads during critical project phases.
• Work across implementation through signoff and tapeout readiness to help customers achieve first-pass silicon success.

Requirements

Must-have technical skills and experience to perform the role effectively. Nice-to-have items are listed separately.

• Must-have: Direct experience with RTL-to-GDS implementation flows, including synthesis, place-and-route, timing closure, and physical design optimization.
• Must-have: Strong working knowledge of Fusion Compiler, ICC2, or equivalent digital implementation tools.
• Must-have: Practical understanding of timing, power, congestion, routing, and design closure methodologies.
• Must-have: Proficiency in scripting with TCL and Python to automate design tasks and improve workflow efficiency.
• Must-have: Ability to engage directly with customers (senior engineers and managers) and communicate technical concepts clearly; business-level English.
• Must-have: Demonstrated use of AI tools and automation technologies to improve engineering productivity and problem solving.
• Nice-to-have: Working knowledge of signoff and verification tools such as Formality and PrimeTime.
• Nice-to-have: Experience with advanced process nodes (7nm and below) and familiarity with issues that arise at 5nm/3nm.
• Other: Willingness to travel or engage onsite with customers as required.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, plus at least 5 years of hands-on ASIC, physical design, implementation, or CAD engineering experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.