Staff Application Engineer - Physical Design
SynopsysJob Title
Staff Application Engineer - Physical Design
Role Summary
Senior technical applications engineer working with semiconductor customers to resolve complex RTL-to-GDS physical design issues and drive successful tapeouts using Synopsys physical design tools (Fusion Compiler, ICC2, Design Compiler).
Part of the Customer Success Group; primary mission is to deliver methodology recommendations, on-site support, and tooling expertise to help customers meet PPA and schedule targets at advanced nodes.
Experience Level
Senior-level. The role expects substantial hands-on ASIC physical design experience; the source lists degree-plus-experience guidance (see Education Requirements).
Responsibilities
Primary customer-facing and technical responsibilities:
- Support customer engagements on Fusion Compiler, ICC2, and Design Compiler to help achieve PPA targets on advanced-node designs.
- Debug complex physical-design issues across placement, CTS, routing, timing closure, and power optimization.
- Develop and deliver tailored methodology recommendations based on customer constraints, process technology, and schedules.
- Run benchmarks and proof-of-concept flows to demonstrate tool capabilities and AI-driven optimization features.
- Collaborate with R&D, product management, and field teams to convert customer pain points into product requirements.
- Present technical content to customer engineering teams and management, linking technical changes to business outcomes.
- Travel to customer sites as needed for onsite support, training, and design reviews.
Requirements
Key technical skills and experience required (must-haves first):
- Deep experience with RTL-to-GDS flows, including placement, optimization, CTS, and routing at advanced nodes.
- Hands-on experience with Synopsys backend tools, specifically Fusion Compiler or ICC2, including timing closure, macro placement, and routing.
- Proficiency with static timing analysis tools such as PrimeTime, including setup/hold and noise analysis.
- Solid understanding of advanced-node design challenges (FinFET effects, multi-patterning, electromigration) and their impact on PPA.
- Experience with logical and physical synthesis flows and familiarity with AI-driven optimization methodologies.
- Strong communication and presentation skills for technical and management audiences.
- Ability to triage high-severity customer issues, manage multiple engagements, and document work for seamless handoffs.
Education Requirements
Bachelor's degree in Electrical Engineering (or equivalent) with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ years. Equivalent practical experience is accepted per the original posting.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
