Staff Analog Mixed-Signal Design and Modelling Engineer

Job Title

Staff Analog Mixed-Signal Design and Modelling Engineer

Role Summary

Join the Cryo-CMOS IC team in Oxford to design analog and mixed-signal ASIC blocks and to own full-chip modelling and integration. The role covers specification, circuit design, simulation, layout, tape-out and silicon validation, and building mixed-abstraction models (transistor-level, Verilog-A/Verilog-AMS and real-number SystemVerilog) used for verification from room temperature to cryogenic operation.

Location: Oxford office with an option for several remote days per week. Travel up to 5%.

Experience Level

Senior-level — typically 10+ years of relevant analog and mixed-signal design and modelling experience.

Responsibilities

Design, model and verify analog/mixed-signal blocks and maintain a full-chip mixed-abstraction model used across the IC development flow.

• Define and own the full-chip modelling strategy: architecture, abstraction levels, accuracy targets and sign-off criteria.
• Design precision analog/mixed-signal blocks (references, DACs, regulators, switches, clock distribution) from specification through schematic and layout.
• Develop Verilog-A and Verilog-AMS models of analog blocks and assemble them into a simulatable full-chip model.
• Create real-number SystemVerilog models for digital verification and regression at practical speeds.
• Derive models from first-principles mathematics and validate them against schematics and measured silicon.
• Perform model-versus-schematic correlation and keep models synchronized with design releases and silicon measurements.
• Set up mixed-signal co-simulation and regression (e.g., Cadence AMS Designer, Xcelium with Spectre) including parasitic extraction and post-layout verification.
• Lead block-level design reviews and mentor junior engineers on circuit design and modelling practices.

Requirements

Must-have technical skills and experience required for the role.

• Deep analog and mixed-signal design and modelling experience with multiple production tape-outs and silicon bring-up responsibility.
• Expert transistor-level design of precision analog blocks, including PVT and Monte Carlo analysis, layout and silicon validation.
• Proven experience developing production-quality Verilog-A and Verilog-AMS models and real-number SystemVerilog models.
• Fluency in a production Cadence flow (Virtuoso, Spectre) and experience with co-simulation tools (AMS Designer, Xcelium) and parasitic extraction.
• Strong mathematical foundation: linear systems, Laplace and z-domain analysis, network (Z-) parameters, noise and non-linearity.
• Experience with MATLAB or Python/NumPy for analysis and model validation; scripting to automate model generation and regression.
• Ability to judge modelling fidelity, align cross-functional teams on model expectations, and define sign-off criteria.
• Nice-to-have: cryogenic, space, or other extreme-environment silicon experience when operating beyond foundry model validity.

Education Requirements

Not specified.

About the Company

Company: IonQ

Headquarters: College Park, Maryland, United States

Quantum computing company developing integrated quantum systems for computing, networking, sensing, and security. Provides quantum hardware and services to cloud providers and enterprise customers across industries including drug discovery, materials science, and defense.