Staff Analog Design Engineer, SerDes Clocking

Job Title

Staff Analog Design Engineer, SerDes Clocking

Role Summary

Responsible for transistor-level analog design and ownership of the clocking subsystem for high‑speed SerDes IO chiplets, including PLL, DLL, phase interpolator, clock distribution, and CDR loop. Works across specification, circuit design, layout, verification, and silicon bring-up, partnering with datapath, DSP, digital, and firmware teams.

Hands-on role focused on meeting jitter and timing budgets and delivering production silicon in advanced process nodes.

Experience Level

Senior level; requires 5+ years of hands-on analog and mixed-signal circuit design experience.

Responsibilities

Design, verify, and deliver clocking-related blocks for SerDes links:

• Architect and implement low‑jitter PLLs (LC or ring), VCOs, dividers, loop filters, and charge pumps/digital loops.
• Design phase interpolators and phase-rotation schemes; manage INL/DNL, glitches, and resolution requirements.
• Design high‑frequency clock distribution: buffer chains, duty-cycle correction, quadrature generation, skew control, and supply/substrate isolation.
• Define and verify CDR architecture and loop dynamics; model behavior in MATLAB/Python and correlate with transistor-level and silicon results.
• Build phase-noise and jitter budgets and identify dominant jitter sources.
• Create verification environments: PSS/HB, transient noise, PVT corners, Monte Carlo, and post-layout simulations; provide behavioral and Verilog-A models.
• Drive layout in deep sub‑micron nodes with attention to inductor/VCO layout, shielding, symmetry, and isolation.
• Lead silicon bring-up and bench characterization (phase noise, jitter tolerance, lock range) and correlate measurements with simulations.

Requirements

Key must-have skills and experience:

• Proven ownership of a low‑jitter PLL, phase interpolator, or CDR loop through silicon in a high‑speed SerDes link.
• Deep understanding of PLL architecture, loop dynamics, VCO design, and phase noise theory; working knowledge of CDR architectures and jitter analysis.
• Practical experience with jitter decomposition and budgeting methodology.
• Circuit design experience in advanced FinFET or GAA process nodes using industry-standard analog tools (e.g., Cadence Virtuoso, Spectre) and simulation methodologies (Monte Carlo, post-layout).
• Silicon bring-up and bench debug experience with lab equipment such as phase noise analyzers, high-speed oscilloscopes, and BERTs.

Nice-to-have:

• Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY) and related clocking architectures.
• Forwarded-clock, matched-source-synchronous architectures, and embedded-clock CDR experience.
• Digital or hybrid PLL/CDR implementations and calibration techniques.
• Familiarity with standards: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7.
• Experience porting clocking blocks across process nodes or contributing to standards bodies.

Education Requirements

BS, MS, or PhD in Electrical Engineering (BS/MS/PhD in Electrical Engineering) as stated in the posting.

About the Company

Company: d-Matrix

Headquarters: Santa Clara, California, United States

d-Matrix is a Santa Clara–based startup developing highly programmable in-memory computing architectures and accompanying software to accelerate generative AI and other AI workloads, focusing on hardware-software co-design for cloud and edge applications.