Staff AMS Layout Engineer - DPG LPDDR

Job Title

Staff AMS Layout Engineer - DPG LPDDR

Role Summary

Lead and execute custom analog and mixed-signal physical layout for LPDDR PHY blocks (datapath, bias, IO front ends, reference circuits) at advanced process nodes. Drive layout integration, verification, and PPA improvements to enable first-pass silicon success and high-volume manufacturability.

Experience Level

Senior — 10+ years of hands-on experience in custom analog and high-speed layout design, particularly for LPDDR or similar high-speed memory interfaces.

Responsibilities

Accountable for end-to-end layout delivery, signoff, and mentoring within the PHY/layout team.

• Own custom analog and mixed-signal layout for LPDDR PHY blocks (datapath, IO, bias, reference circuits).
• Lead high-speed LPDDR interface layout: skew control, impedance matching, shielding, crosstalk mitigation, jitter sensitivity.
• Architect scalable, symmetric array-based layouts for DQ/DQS, CA lanes, and replica paths.
• Integrate custom digital and mixed-signal blocks ensuring clocking, congestion management, and isolation.
• Drive layout-aware co-design with circuit, verification, architecture, and silicon debug teams.
• Define power distribution, grounding, isolation strategies (guard rings, deep N-well, decoupling, domain separation).
• Lead physical verification and signoff: DRC/LVS, parasitic extraction, and simulation correlation.
• Execute post-layout optimization and ECOs to resolve margin, yield, and manufacturability issues (JEDEC compliance).
• Mentor engineers and establish layout methodologies, flows, and best practices.

Requirements

Must-have technical skills and experience required to perform the role.

• 10+ years of hands-on custom analog and high-speed layout experience at advanced nodes.
• Proven LPDDR (LPDDRx) or equivalent high-speed interface layout expertise, including signal integrity and timing concerns.
• Strong knowledge of analog layout techniques: matching, low-noise design, shielding, and isolation.
• Experience with layout signoff flow: DRC/LVS, parasitic extraction and correlation to circuit performance.
• Power distribution, grounding, and EM/IR-aware layout experience.
• Scripting for automation (SKILL, Python, TCL) to improve productivity and flow integration.
• Experience driving PPA optimizations and post-layout ECOs for manufacturability.
• Demonstrated ability to lead cross-functional co-design and mentor junior engineers.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.