STA/Timing Methodology Engineer (Lead/Staff)

Job Title

STA/Timing Methodology Engineer (Lead/Staff)

Role Summary

Lead/Staff STA/Timing engineer responsible for timing methodology, sign-off and convergence for complex SoCs. The role focuses on STA setup, timing analysis and debug, methodology development, and automation to ensure timing closure across multiple modes, voltages and PVT corners.

Experience Level

Senior — typically 6–10 years of hands-on STA/timing sign-off and methodology experience; expects demonstrated experience driving timing convergence on large chip designs.

Responsibilities

Primary responsibilities include timing sign-off, flow development, automation and cross-functional coordination.

• Set up, converge, review and sign off STA for multi-mode, multi-voltage domain designs.
• Perform timing analysis, validation and debug across PVT corners using PrimeTime and/or Tempus.
• Run STA flows and optimize them; correlate Spice simulations to STA results.
• Evaluate and recommend timing methodologies and tools across designs and technology nodes.
• Develop automation and scripts within STA/PD tools to support methodology development.
• Collaborate with physical design (PD) and methodology teams across sites to achieve timing closure.
• Document methodology, present findings, and communicate technical status to stakeholders.

Requirements

Must-have technical skills and experience to perform the role; nice-to-have items follow.

• Must-have: Substantial hands-on STA/timing sign-off experience using PrimeTime and/or Tempus, including chip-level and hard-macro timing convergence.
• Must-have: Strong knowledge of timing concepts (AOCV/POCV, CTS, timing constraints, latch transparency, 0-cycle and multi-cycle paths).
• Must-have: Experience with STA flows for multi-mode/multi-voltage designs and analysis across PVT corners.
• Must-have: Proficiency scripting in TCL, Perl, or Python for flow automation.
• Must-have: Familiarity with digital backend implementation flows and tools (RTL-to-GDS: ICC / Innovus) and interaction with PD teams.
• Must-have: Experience correlating circuit simulations (Hspice / FineSim) to STA and using Monte Carlo for variability analysis.
• Must-have: Strong technical writing and communication skills; ability to work in cross-collaborative, multi-site teams.
• Nice-to-have: Basic device physics knowledge and deeper experience in signal integrity (crosstalk), layout parasitic extraction and feed-through handling.
• Nice-to-have: Prior involvement in process technology enablement or silicon-to-spice model correlation.

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering or a related engineering field is listed; Master's (MTech/MS) or PhD in Computer Science, Electrical/Electronics, Microelectronics, VLSI or related fields are also referenced as acceptable qualifications. Specific mentions include B.Tech and MTech/MS in Electrical/Electronics/Microelectronics/VLSI.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.